Architecture And Synthesis For Dynamically Reconfigurable Asynchronous Fpgas

Abstract

The current slowdown in CMOS technology scaling presents opportunities for architectural innovation, in particular augmentation of general purpose processors with specialized units. Self-timed field-programmable gate arrays (FPGAs) are attractive in this space because of their high throughput, robustness, and modularity. In my thesis, I present an architecture for a dynamically reconfigurable asynchronous field-programmable gate array, describe efforts to limit the overheads of asynchronous communication in the context of 3D integration, and develop an asynchronous-aware toolflow for mapping designs to the FPGA.