Static Power Reduction Techniques For Asynchronous Circuits
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Power gating techniques are effective in mitigating leakage losses, which represent a significant portion of power consumption in nanoscale circuits. We examine variants of two representative techniques, Cut-Off and Zig-Zag Cut-Off [12], and find that they offer an average of 80% and 20% in power savings, respectively, for asynchronous circuit families. We also present a new zero-delay (ZDRTO) wakeup technique for power gated asynchronous pipelines, which leverages the robustness of asynchronous circuits to delays and supply voltage variations. Our ZDRTO technique offers a trade off between wake up time and static power reduction, making it suitable for power gating pipelines with lowduty cycle, bursty usage patterns.
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2012-08-20
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Asynchronous; static power; vlsi; Integrated Circuits; leakage
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Manohar, Rajit
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Myers, Andrew C.
Suh, Gookwon Edward
Suh, Gookwon Edward
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Electrical Engineering
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M.S., Electrical Engineering
Degree Level
Master of Science
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Government Document
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dissertation or thesis