Static Power Reduction Techniques For Asynchronous Circuits
| dc.contributor.author | Ortega Otero, Carlos | en_US |
| dc.contributor.chair | Manohar, Rajit | en_US |
| dc.contributor.committeeMember | Myers, Andrew C. | en_US |
| dc.contributor.committeeMember | Suh, Gookwon Edward | en_US |
| dc.date.accessioned | 2013-01-31T19:43:53Z | |
| dc.date.available | 2017-12-20T07:00:28Z | |
| dc.date.issued | 2012-08-20 | en_US |
| dc.description.abstract | Power gating techniques are effective in mitigating leakage losses, which represent a significant portion of power consumption in nanoscale circuits. We examine variants of two representative techniques, Cut-Off and Zig-Zag Cut-Off [12], and find that they offer an average of 80% and 20% in power savings, respectively, for asynchronous circuit families. We also present a new zero-delay (ZDRTO) wakeup technique for power gated asynchronous pipelines, which leverages the robustness of asynchronous circuits to delays and supply voltage variations. Our ZDRTO technique offers a trade off between wake up time and static power reduction, making it suitable for power gating pipelines with lowduty cycle, bursty usage patterns. | en_US |
| dc.identifier.other | bibid: 7959712 | |
| dc.identifier.uri | https://hdl.handle.net/1813/31005 | |
| dc.language.iso | en_US | en_US |
| dc.subject | Asynchronous | en_US |
| dc.subject | static power | en_US |
| dc.subject | vlsi | en_US |
| dc.subject | Integrated Circuits | en_US |
| dc.subject | leakage | en_US |
| dc.title | Static Power Reduction Techniques For Asynchronous Circuits | en_US |
| dc.type | dissertation or thesis | en_US |
| thesis.degree.discipline | Electrical Engineering | |
| thesis.degree.grantor | Cornell University | en_US |
| thesis.degree.level | Master of Science | |
| thesis.degree.name | M.S., Electrical Engineering |
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