This thesis consists of two central goals. The first goal is to introduce an analog-todigital converter (ADC) in time-domain resolutions. With the down scaling of the minimal feature size of modern submicron CMOS technologies, time-to-digital conversion (TDC) is found very useful in many applications as well as analog-todigital converters. This is the case when it is profitable to replace badly scaling analog circuits with time-to-digital conversions. Since technology scaling implies voltage scaling while noise does not scale along, variability becomes more important. This requires more effort to be put into analog circuits that mostly leads to increased power consumption. However, digital speed does scale with technology. Since time-domain converters directly profit from enhanced speed performance, switching from the analog to the digital time domain can significantly reduce the power consumption for equal performance, especially for designs in sub-100nm technologies. In general, Analog-to-Digital conversion is performed in three steps: signal difference amplification, a zero crossing detector, and a succeeding logic encoder. The signal difference amplification is performed by amplifying the analog voltage (or current) level by a voltage (or current) amplifier. However, due to the device and voltage scaling in the CMOS technology, signal difference amplifications become more challenging to achieve low power consumption with high gain. For a time-domain ADC, as a different solution for signal difference amplification, delay amplification is used. In the first chapter, in order to verify the benefit from a time-domain ADC, a 125 MS/s 8bit delay-line based ADC is studied and implemented as a circuit using TSMC 65 nm CMOS process. Simulation results show that, with 1.95 MHz sinusoidal input, the ADC achieves 7.45 ENOB, a peak differential nonlinearity of 0.095 least significant bit (LSB), and a peak integral nonlinearity of 0.809 LSB with the power dissipation of 1.8 mW from a 1.2 V supply voltage. The second chapter studies the pulse generation in electrical LC lattice. When input voltage sources are applied to a two-dimensional nonlinear LC lattice, a constructive interference results in an output signal at the center node with boosted amplitude and sharpened pulse width compared to its original input signal. The chapter is focused on the theoretical and experimental study of certain nonlinear wave synthesis phenomena that appear on the two-dimensional nonlinear LC lattice. It is demonstrated how the nonlinearity can help in synthesizing high frequency and high amplitude wave pulse at the central nodes of the lattices. The LC lattice is implemented on PCB composed of voltagedependent capacitors and inductors, and for the intense nonlinearity, the capacitor is carefully chosen. At one horizontal and one vertical boundary, respectively 20 sinusoidal input sources are applied in phase. The peak-to-peak input amplitude is 1 V, and the frequency is 13.5 MHz, and the offset voltage for the voltage-dependent capacitor is 200 mV. Measurement results show that the amplitude is boosted to 7.5 V and the pulse width of the signal is narrowed from 74 ns to 14 ns at the central node.