TOWARDS LOW NOISE, HIGH POWER AND EFFICIENCY MM-WAVE AND TERAHERTZ CIRCUIT DESIGN
Mm-wave and terahertz frequency range is gaining vast attention in recent years due to attractive applications in various areas including spectroscopy, imaging, security and high data-rare communication. All these systems require high performance circuits for power generation and ampliﬁcation. In recent years, many ampliﬁers and oscillators have been fabricated in SiGe and CMOS processes to show the feasibility of implementing these systems in this frequency range. Despite all the efforts and ideas employed to enhance the performance of these blocks, there is still a long way to go to achieve reasonably high performance ampliﬁers and signal sources at mm-wave and terahertz frequencies. The main challenge comes from the activity degradation of the transistors, high loss in the passives and high noise in the active and passive devices at this frequency range. In this work, new systematic design methods for low noise and highgain ampliﬁers and high power and efﬁciency oscillators at mm-wave and terahertz frequencies are presented. Chapter 1 reviews the basic concepts of the two-port networks such as stability, activity, power gains and noise parameters. These subjects are vastly used in the next chapters of this work when presenting the new methods for high frequency circuit design. In chapter 2, a new convex stability region is presented based on which, a systemic ampliﬁer design method beyond fmax/2 is proposed which moves the network toward the high gain region using optimum passive embeddings. This method is capable of considering modeling errors of the components during the design process which results in a robust, stable and high gain ampliﬁer. Employing this method, a three stage ampliﬁer working at 173 GHz is designed and implemented in a 130 nm SiGe process which shows 18.5 dB gain, 8.2 GHz 3-dB bandwidth and 0.9 dBm saturated output power in the measurement. A new FoM is deﬁned to fairly compare different ampliﬁers fabricatedindifferentprocesseswhichtargetsthecapabilityofthedesignmethodinextracting the power ampliﬁcation potential of the active device. This ampliﬁer achieves the highest FoM among all reported state of the arts works above fmax/2 in SiGe/CMOS processeswhichshowstheefﬁcacyoftheproposedmethodinfullyutilizingtheprocess capabilities in ampliﬁer design. In chapter 3, high frequency LNA is targeted and a systematic method to design low noise and high gain ampliﬁer beyond fT/2 is presented. To achieve this goal, noise measure of the proposed structure becomes minimum employing optimum passive embeddings while the stability of the circuit is assured using the convex stability region derived in chapter 2. The guidelines and required noise and power equations to complete the systematic LNA design are derived and presented in this chapter. Employing this method,a 91 GHz LNA with 5.6dB noise ﬁgure,9.7 dB gain and 6.3 mW dc power consumption is implemented in a 130nm SiGe process. Comparing these results with the state of the arts using the proposed FoM that takes the process and power consumption into account justiﬁes the effectiveness of this design method in fully utilizing low noise and high power generation capability of the process. A design methodology for high power mm-wave VCO design is presented in chapter 4. Using the complete passive embeddings including the load, the power gain from the input of the active device to the load is maximized which results in an oscillator with high power at the output and signiﬁcantly improved DC-to-RF efﬁciency. In addition, the proposed structure is capable of providing sufﬁcient tuning range which is an important factor in mm-wave source design and applications. A VCO working at 110 GHz is designed and implemented in a 55 nm SiGe process employing this method which shows 6.3 dBm peak output power, 20.9% DC-to-RF efﬁciency and 5.2% tuning range. This VCO achieves highest peak output power in F and D band (90 GHz to 170 GHz) and highest DC-to-RF efﬁciency in frequencies below fmax/2 among all reported mm-wave oscillators in SiGe/CMOS processes. Chapter 5 represents a new design method for high power and efﬁciency harmonic oscillator. This method exploits different mechanism to enhance the fundamental oscillator performance, increasing the harmonic power generation in the active device and effectively delivering the generated harmonic power to the load using various passive embeddings in a cross-coupled structure. Capacitive degeneration is employed to shape Gm of the structure. Inductive embeddings at the base of the transistors are utilized to provide sufﬁcient voltage gain and increase harmonic current generation in the active device. The embeddings at the collector are used to maximize the output resistance of the structure which results in delivering majority of the generated current to the load. Employing this method, a 300 GHz harmonic oscillator is designed and implemented in a 130 nm SiGe process which shows 2.8 dBm peak output power and 4.5% DC-to-RF efﬁciency with 86.6 mW/mm2 power-area efﬁciency. Also, a harmonic VCO is implemented with 2.3 dBm peak output power, 3.5% DC-to-RF efﬁciency and 1.5% tuning range and 77.2 mW/mm2 power-area efﬁciency in the same process. This harmonic oscillator method signiﬁcantly improves the power-area efﬁciency of high frequency signal sources and the designed oscillator achieves the highest power-area efﬁciency among all reported SiGe/CMOS oscillators working above 0.75 fmax.
High frequency circuit; LNA; mm-wave and Terahertz; VCO; amplifier; Engineering; Harmonic Oscillator
Apsel, Alyssa B.; Pollock, Clifford Raymond
Electrical and Computer Engineering
Ph. D., Electrical and Computer Engineering
Doctor of Philosophy
dissertation or thesis