Hybrid Memories For Energy Efficient Computing Systems

Abstract

To sustain processor performance, demand for memory capacity and bandwidth continues to grow. Computer architects use different memories, structured in a hierarchy, to build memory systems to satisy that demand. Architects design hierarchies to take advantage of trade-offs inherent to the different memory technologies available. New memory technologies, such as non-volatile memories, bring different trade-offs into the design space. Interestingly, non-volatile memory technologies have a set of trade-offs that complement existing memory technology well. As a result, architects have proposed hybrid memory designs, using both traditional and new memories in the same memory structure, to exploit memory technology advantages and mitigate their disadvantages. Using disparate memories in tandem, at the same level of hierarchy, can unlock efficiencies and new capabilities unseen with monolithic memory arrays. In this thesis I describe and categorize a landscape of hybrid memory organizations, and then describe 3 concrete projects we undertook to demonstrate the advantages of certain hybrid organizations. I discuss a hybrid SRAM-Flash memory that reduces energy usage and brings non-volatile save and restore operations within reach of energy-limited platforms, a hybrid SRAM-DRAM memory that can replace SRAM-only register files with the same capacity and performance but at reduced area and energy costs, and a hybrid SRAM-MRAM cache using compression to reduce overall cache energy.