Analysis And Design Of Hybrid Ferroelectric-Cmos Circuits

Abstract

The demand for energy efficient microprocessors has stimulated research into nonvolatile logic design, with ferroelectrics (FE) as the prime candidate technology. In spite of the large FE polarization compared to CMOS charge, present hybrid designs show low differential signals. In this thesis, the question of signal improvement in hybrid FE-CMOS circuits is explored with physical modeling, simulations and experiments. To simulate FE behavior with arbitrary voltage or current input signals, we present a unified physical model of polarization switching based on the stochastic geometry of nucleation and growth. The model is first constructed for ideal FE capacitors with infinite area, and then extended to include the realistic effects of device scaling, domain growth anisotropy, disorder, imprint and fatigue. Circuit predictions for three classes of FE nonvolatile latches are experimentally verified. Design intuition for signal timing, sensing margins and reliability degradation in each topology is presented. The design space limitations are analysed and two new techniques with improved differential signals, mismatch and imprint tolerance as well as FE layout area requirement are proposed and experimentally verified. A novel single-transistor memory is proposed which combines the complementary characteristics of FE and flash memory. The FE polarization dynamics naturally establish a two-step process - fast FE switching followed by slow charge injection. This proposal is evaluated with simulations and verified with device fabrication and measurements.