A Workload Adaptive Voltage Scaling Multiple Clock Domain Architecture
This thesis presents a comprehensive system for allowing a Multiple Clock Domain (MCD) processor to adapt to its workload in an efficient manner. We present adaptive techniques at both the architecture and software levels. These techniques allow our system to either meet specified throughput demands while consuming as little energy as possible, or to stay within an average power budget while providing the highest possible throughput. We first present an architecture-level adaptive system. This system adapts the voltage/frequency configuration of the MCD processor to meet the workload of a single application efficiently. As its input, this system can take either a throughput goal to meet using the least possible energy, or an average power level to remain below. We also show that our adaptive system can give an MCD processor increased tolerance to changes in performance and power dissipation due to variations. Next, we extend this adaptivity to multiprogrammed workloads. We present a scheduling algorithm that considers the throughput goals of each running application. Using this feedback, it schedules the applications in such a way as to minimize total energy consumption without altering the throughput of the individual applications. Finally, we present a system that allows individual applications to determine their throughput by comparing their actual progress to their desired progress rate. This system acts as a bridge between our architectural and inter-program adaptive systems. Each application's desired throughput is used in two ways. First, this throughput becomes the target throughput for our architecture-level system. Second, this throughput information provides the feedback that allows our scheduler to determine how it should schedule the application workload to minimize energy.
low power; voltage scaling; multiple clock domains; computer architecture; variations
Dissertation or Thesis