Zhang, Danfeng; Wang, Yao; Suh, G. Edward; Myers, Andrew C.
Timing channels pose a real security risk, but methods are lacking for building systems without timing leaks. One reason is that low-level hardware features create timing channels; for example, caches enable probing attacks. We introduce a new hardware design language, SecVerilog, that in conjunction with software-level enforcement makes it possible to build systems in which timing channels and other leakage are verifiably controlled. SecVerilog extends Verilog with annotations that support comprehensive, precise reasoning about information flows at the hardware level. Compared to previous methods for designing secure hardware, SecVerilog offers a better tradeoff between expressiveness and run-time overhead. We demonstrate that it is expressive enough to build complex hardware designs, including a MIPS processor, with low overhead in time, space, and programmer effort. Information flow checking is mostly static, permitting hardware designs that are largely unaffected by security enforcement mechanisms. SecVerilog also tracks information at fine granularity, allowing interleaving of instructions and data at different security levels throughout the processor. SecVerilog also comes with stronger formal assurance than previous hardware design methods: we prove that it enforces noninterference, ensuring secure information flow.
Content file updated by author on 15 January 2015.
Office of Naval Research (N00014-13-1-0089) the MURI grant (FA9550-12-1-0400), the Air Force grant (FA8750-11-2-0025), the National Science Foundation grants (CNS-0746913, CCF-0905208, CCF-09644909), and a grant administered by the Air Force Research Laboratory.
timing channels; information flow; hardware description language