Practical Nano-Mechanical Devices For Electronic Applications
The increasing difficulty in the scaling of Complementary Metal Oxide Semiconductor (CMOS) devices has given rise to a corresponding increase in the interest of alternate and novel approaches to switching at the nanoscale. Reducing critical dimensions of nanoscale devices has resulted in highly non-ideal switch performance and greater variability of switch characteristics within an ensemble of devices. Solutions to these difficulties have led to an immense increase in complexity of CMOS design and fabrication. The challenges posed by further size reduction stem from large scale and small scale effects. At the small scale we have quantum effects, and stochastic effects arising from discreteness and noise, and the large scale has thermodynamic issues of large numbers of devices. Two key features of CMOS have seen diminishing returns at the nanoscale: threshold voltage and leakage currents. Smaller devices are less efficient individually and are more difficult to control the on/off switching behavior. Additionally, variability amongst smaller devices has increased the likelihood of device failure or operation outside acceptable design rules. For instance, line edge roughness of optical lithography and dopant fluctuation of implantation have been large sources of inconsistency in fabrication. Therefore, fundamental challenges lie in further scaling, whether through physical laws or material difficulties. And although smaller devices have improved density and speed of integrated circuits, the power density has also increased; whereby thermal management has become a primary difficulty. This myriad of problems is a natural manifestation of more than four decades of device improvement based solely on the enhancement of standard silicon CMOS technology. It is inevitable that silicon technology will hit an ultimate size limit, and being that silicon is still host to the best combination and balance of electronic, mechanical, and material properties, there is great incentive in finding a means to reach the ultimate scalability of silicon. Two approaches are considered for continuing scaling; increasing functionality of CMOS by heterogeneous integration of other technologies, or a paradigm shift away from CMOS. At this point there is no other clear alternative. And with a mature silicon technology, it can be extremely advantageous to incorporate suitable alternate technologies with CMOS to enable further scaling. NanoElectroMechanical Systems (NEMS) of the electrostatic variety have two great advantages to CMOS: zero current leakage and zero subthreshold swing. Although electromechanical switches have been previously suggested for logic, memory, and reconfigurable applications, all previous approaches have utilized either a top down planar approach, or a bottom up vertical approach. Planar approaches suffer from area constraints do to the bending stiffness of the mechanical element. And vertical approaches are limited by variability in growth based structures and other non-CMOS compatible processes. We suggest a new device structure that merges the best of both approaches to create the first top down vertical device. This structure enables the ultimate scalability of NEMS devices and opens the door to potential integration with CMOS via 3D integration. The simple single step lithography fabrication can enable a mechanical device on the scale of CMOS to be useful for error correction; faults and defects inherent to the final nodes of CMOS technology can be potentially rerouted and removed from the signal path, thereby retaining functionality of the greater system.
NEMS; Nanorelay; Torsion
McEuen, Paul L.; Buhrman, Robert A
Ph.D. of Electrical Engineering
Doctor of Philosophy
dissertation or thesis