With the explosion of information hungry computational and multimedia applications, the need for exceptionally high communication data rates has leapt to the forefront of electronic design. Advances is silicon technologies, manifested both in the speed of the transistors and complexity of the IC wiring stack, has bolstered the ability to meet new communication needs on a platform common to most consumer electronics. This ability becomes beneficial to historical approaches, both in system performance and costs, with the later being a huge benefit over existing solutions. In this work the design of high speed wireless and wired communications on silicon platforms is investigated. The work uses both standard silicon CMOS technologies and silicon germanium BiCMOS technologies to demonstrate operations beyond 100 GHz and 100 GB/s. Activities in the wireless domain investigate both receivers and transmitters up to 100 GHz, with the most substantial work performed on the design and analysis of voltage controlled oscillators and low noise amplifiers. Differential and quadrature VCOs have been designed for operation between 16-64 GHz, with innovation in design methodologies and varactor degeneration. LNA design has been performed for operation from 20-110 GHz, with emphasis on balanced/unbalanced operations. Wireline development has focused on the design of two parallel systems for operation beyond 80 GB/s and 120 GB/s. Parallel development of half-rate 4 to 1 multiplexers and 1 to 4 demultiplexers has been performed, as well as development of a 60 GB/s full rate flip-flop and 60 GHz static divider. Aggressive clocking techniques were developed to enable broadband operation from below 1 GB/s to the upper frequency bounds, and an area-centric design methodology was developed to mitigate the common perils of high frequency design. Collectively, the circuits demonstrated here show a methodology aimed at enabling high frequency design despite the hurdles inherent in silicon processes. Most of these techniques are aimed at combating the limitations of the silicon substrate, even beyond the frequency limitations of the devices, and towards overcoming the amplified effects of interchip wiring at increased frequencies. In many instances the latter effects drive the electrical design of the circuits, where certain conventional techniques for high frequency design become impaired and undesirable.