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  4. Efficient, Robust, and Self-Supervised Algorithm-Hardware Co-Design

Efficient, Robust, and Self-Supervised Algorithm-Hardware Co-Design

File(s)
Meng_cornellgrad_0058F_14977.pdf (59.71 MB)
Permanent Link(s)
https://doi.org/10.7298/wpfm-5k07
https://hdl.handle.net/1813/117605
Collections
Cornell Theses and Dissertations
Author
Meng, Jian
Abstract

The development of artificial intelligence has revolutionized human society. Computer vision and natural language processing have demonstrated superior performance across a wide range of tasks. From a performance standpoint, the rise of scaling laws has come at the cost of significantly increased computational demands in both the pretraining and post-training phases. The persistent challenges of computational complexity, memory overhead, and energy consumption call for system-level efficiency through hardware–algorithm co-optimization and reliable verification toolkit. Although compression methods have been widely investigated for different model architectures and tasks, jointly optimizing algorithms and specialized AI hardware shows tremendous promise and urgent necessity for both edge- and cloud-based AI computing. Beyond system-level optimization, improving the generality of and understanding the limitations of under-parameterized lightweight model pretraining offers an additional and compelling perspective for efficient AI models and algorithms. Finally, the visual quality degradation resulting from compression and under-parameterized models makes the generative 3D computer vision tasks even more challenging in comparison to the accuracy-driven tasks, whereas the computing and memory resources on VR/AR devices are limited. Motivated by the aforementioned challenges, this doctoral research focuses on the design of efficient and robust AI algorithms and systems, targeting both customized and commercial AI computing platforms for computer vision and language generation applications. Specifically, this dissertation first presents a series of research works based on customized AI In-Memory-Computing (IMC) platforms with Resistive Random Access Memory (ReRAM); as a starting point, this research presents a structured pruning algorithm followed by the dedicated in-memory-computing deployment scheme. While the efficiency has been improved, the non-ideality of the individual ReRAM device and non-reliable retention characteristics destroy the accuracy of the pre-trained model, which motivates the follow-up investigation on algorithm-aided robust enhancement algorithm. In addition to the RRAM-based AI computing, this dissertation also focused on the prue algorithm-level model pruning and efficiency enhancement with supervised and self-supervised learning. For customized hardware, an FPGA-based accelerator is presented with fully-on-chip sparse computing and zero off-chip memory access. On the algorithm side, this research widely explores both supervised and self-supervised sparse training methods, which 1) enable the real-time dynamic sparse model inference and 2) investigate the bottleneck of self-supervised sparse training with contrastive dynamic pruning. Although the various pruning and compression algorithms are widely explored, the compatibility of commercial edge devices are limited. Therefore, directly improving the performance of lightweight models becomes critical. This dissertation presents two novel algorithms which reveals the bottleneck that causes the poor performance of the lightweight model pretraining, focusing on both contrastive learning and masked autoencoder (MAE) training. Apart from the case-by-case customized hardware and algorithm design, this research presents a model compression algorithm designed of drivable 3D Codec Avatar for actual commercial hardware deployment while eliminating the dynamic rendering noises. For the customized hardware, this research introduces Torch2Chip, a generic and end-to-end toolkit for customized hardware-algorithm co-design.

Description
234 pages
Date Issued
2025-05
Committee Chair
Seo, Jae-sun
Committee Member
Abdelfattah, Mohamed
Snavely, Keith
Degree Discipline
Electrical and Computer Engineering
Degree Name
Ph. D., Electrical and Computer Engineering
Degree Level
Doctor of Philosophy
Type
dissertation or thesis
Link(s) to Catalog Record
https://newcatalog.library.cornell.edu/catalog/16938377

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