In recent years, several devices have been proposed to extend the scaling path of the semiconductor industry (i.e., Moore's law). These devices range from purely logic devices to non-volatile devices to hybrid logic and memory single device embodiments. For the non-volatile and hybrid devices, the storage elements include the charge storage, magnetization states, and phase states. It is imperative to create an end-to-end characterization framework capable of evaluating, characterizing, and benchmarking the performance of the proposed devices. This work introduces a device to architecture characterization framework for emerging post-CMOS devices. We develop compact circuit models for several devices and integrate the circuit models into our newly created layout-based characterization framework. We analyze and compare the performance of select devices in RAM and CAM memory arrays using the created framework. The characterization results show that our layout-based characterization approach provides unique insights that would otherwise not be captured by existing analytical and schematic-only based characterization tools.