As modern applications grow increasingly data-intensive and computationally demanding, dataflow accelerators, such as FPGAs and AMD Versal AI-Engine (AIE), are emerging as promising solutions because they enable parallel execution of compute units and allow direct data transfer between units through fast on-chip memory. By avoiding frequent reads and writes of intermediate results to off-chip memory as seen in processors with Von Neumann architectures like CPUs, dataflow accelerators deliver enhanced performance and energy efficiency, making them ideal for applications that require low-latency, real-time processing, and efficient resource utilization. However, achieving high performance with dataflow accelerators is challenging, as it relies heavily on efficient user programming to fully leverage their capabilities.One critical aspect of this programming effort is optimizing data placement, which involves orchestrating data within the hardware's memory hierarchy to ensure the right data is delivered to the compute units at the right time and in a sufficient rate, thereby maximizing memory bandwidth utilization and preventing compute units from stalling for data, keeping them fully occupied. In this dissertation, we first present HeteroFlow, a programming framework that decouples data placement from algorithm specification for FPGAs. HeteroFlow enables developers to customize placement of data across various hardware hierarchies, including host-accelerator, inter-kernel, and intra-kernel levels in a declarative manner. This enables programmers to efficiently manage data across various design levels without restructuring the original algorithm. Next, we present ARIES, a programming framework for heterogeneous dataflow architectures, where different dataflow accelerators, such as FPGAs and AIEs, work together to enhance system performance. ARIES introduces a unified MLIR-based abstraction to capture both AIE and FPGA, allowing the compiler to optimize the system holistically and derive an efficient scheme for inter-accelerator data placement. ARIES also presents a novel tile-based programming model that enables users to easily decompose a kernel into processing elements (PEs) and schedule their execution on actual hardware, which significantly simplifies intra-kernel data placement between PEs. Finally, we introduce FlexFlow, a novel dataflow programming model to capture input-dependent data placement in dataflow architectures. FlexFlow enables users to declaratively define complex input-dependent data placement, such as packet routing or switching, separately from the computational logic defined in the kernels. This approach eliminates the need for programmers to write imperative code to manage low-level implementation details such as I/O arbitration. Instead, FlexFlow generates communication structures tailored for FPGA and AIEs based on user-defined input-dependent data placement schemes.