The solution of an (n+1)x(n+1) Toeplitz system of linear equations on a one-dimensional systolic architecture is studied. Our implementation of an algorithm due to Bareiss is shown to require only $O(n)$ time and $O(n)$ storage, i.e. constant storage per systolic processor. Key words and phrases: Systolic arrays, Toeplitz matrices, linear equations, Bareiss algorithm, VLSI.