The growing cost of moving data through the memory hierarchy has made data movement a dominant bottleneck in modern computing systems. This challenge has become more pronounced as the end of Dennard scaling shifted performance improvements away from higher clock frequencies and toward parallel architectures, further amplifying the cost of data movement. Processing-in-memory (PIM) addresses this problem by bringing computation closer to where data resides. Within this broader space, associative processors (APs) provide a processing-using-memory approach in which computation is realized within content-addressable memory (CAM) arrays through sequences of parallel search and update operations. From this perspective, APs can be viewed as very long vector execution engines that exploit massive data-level parallelism while reducing costly transfers between memory and compute. Despite this promise, existing associative processors face several key limitations. Bit-serial associative arithmetic dominates execution time and constrains throughput. CMOS-based APs incur substantial area overheads, while emerging-memory alternatives introduce write latency and endurance challenges. In addition, decoupled accelerator-style integrations often leave associative arrays underutilized due to command-distribution and data-movement delays. This dissertation shows that associative processors can serve as a practical and scalable foundation for general-purpose processing-in-memory systems when co-designed across system architecture, microarchitecture, and memory technology. To this end, this dissertation presents three complementary architectural contributions. First, PUMICE introduces a tightly integrated CPU–AP architecture that enables instruction-level parallelism and overlap between memory access and associative execution, reducing idle time and achieving up to 2.2× speedup over prior decoupled designs. Second, Hybrid-CAPE addresses the tradeoff between density and efficiency, on one hand, and speed and endurance on the other by combining FeFET and CMOS storage with technology-aware microcode, reducing area by 30% and energy by 11% while maintaining near-CMOS performance. Third, FastAP overcomes the bit-serial bottleneck by enabling bit-parallel associative arithmetic, achieving up to 28.7× faster addition and 21.3× faster multiplication. Together, these contributions address utilization, efficiency, and computational throughput across the associative processing stack. They demonstrate that associative processors can be transformed into efficient, scalable, and programmable architectures for general-purpose data-parallel computing, establishing a compelling path toward post–von Neumann systems in which computation is brought closer to data.