This thesis presents a wire routing methodology that produces custom-quality results. We use a gridless tile-based approach that extends previous works in four main ways. First, it captures all the intricacies of modern design rules, e.g. the difference between contact-to-contact spacing and contact-to-wire spacing. Second, it implements a robust cost model that includes: i) horizontal wire costs, ii) vertical wire costs, iii) via costs, and iv) jog costs. Third, a design-rule correct route is always guaranteed even if the search for the least-cost path is terminated early. Fourth, route ordering is dynamically updated based upon the routability of nodes. The resulting router is shown to route 1.5-11x faster than the Cadence Chip Assembly Router while consuming 6-8x less memory with 5-15% less wiring overhead.