A new alternative device structure for scalable silicon non-volatile memories was investigated. The difficulties in scaling current devices arise from the non-scalability of the gate stack formed by the tunneling oxide, floating gate and control oxide. The proposed device is based on storage of charge in silicon nitride traps in the back of a thin single crystal silicon channel. This is intrinsically different from conventional silicon non-volatile memory structures, in which charge is stored between the silicon channel and the gate. The devices are fabricated on a modified silicon-on-insulator substrate that employs a stack of silicon oxide ? silicon nitride ? silicon oxide as the buried insulator. The charge trapping layer, silicon nitride, is separated from the silicon channel by a thin tunneling oxide and from a back gate by a thicker blocking oxide. The device is written and erased by applying an electric field between the back gate and source and drain that causes charge to tunnel between the silicon channel and the trapping layer. When there is no voltage applied, charge is retained in the silicon nitride, hence the non-volatility of the memory. Charges stored in the silicon nitride traps change the potential of the silicon channel resulting in a threshold voltage shift of the device that is sensed using the front gate. The decoupling of the read function (front) from the write and erase functions (back) gives this device a unique advantage in scalability and the ability to operate simultaneously as a high performance transistor and as a non-volatile memory. Back side charge trapping non-volatile memory devices were demonstrated for the first time. The fabrication process is described and the electrical characteristics are presented. Fabricated devices exhibit memory operation down to 50 nm gate length and double gate operation down to 20 nm gate length. The memory characteristics of the devices, programming times, cycling endurance and retention time are comparable to those of conventional front side storage devices. The new device has the potential to be scaled to 10 nm gate length, a significant improvement from current devices, for higher density and lower power semiconductor non-volatile memory.