Semiconductor scaling now demands sub-10 nm patterning and sub-nanometer dopant control—requirements that strain the cost and accuracy limits of extreme-ultraviolet (EUV) lithography and conventional TCAD process simulators. This dissertation develops two complementary, simulation-driven pathways to overcome those barriers.First, a coarse-grained molecular-dynamics (MD) framework is used to map the process window for PS-b-PMMA directed self-assembly (DSA) on chemo-epitaxial, brush-coated substrates. Systematic sweeps of pinning-site radius, brush height, and graft density reveal a cooperative confinement regime: brush heights of 2–4 σ combined with pinning radii of 6–8 σ maximize six-fold bond-orientational order (ψ₆ > 92 %), suppress line-edge roughness to < 1 σ (three-sigma envelope), and eliminate pillar tapering. Relative to an unpatterned substrate, optimal flat-pin templates raise ψ₆ from 88.7 % to > 91 %, underscoring the cost-saving potential of DSA as a partial substitute for EUV multiple patterning. Second, a quantum-informed, multi-process MD workflow couples density-functional-theory-derived Si–B Lennard-Jones parameters with a Tersoff Si potential to track boron implantation, pre-deposition, and rapid-thermal annealing in a single LAMMPS environment. The model reproduces 3 keV SIMS profiles for 1 × 10¹⁶ cm⁻² and 5 × 10¹⁵ cm⁻² implants to within ± 5 % over 0–15 nm—more than twice the accuracy of SRIM-based predictions. A 1 nm amorphous B capping layer boosts near-surface concentration by ≈ 35 % without widening the 10–90 % junction depth, while a 950 °C, 8 M-step spike anneal removes ≈ 46 % of vacancies and ≈ 42 % of interstitials, balancing activation against defect regeneration. Collectively, the framework delivers sub-nanometer junction accuracy, explicit defect chemistry, and seamless process integration, opening a predictive route for co-optimizing implant dose, energy, surface treatments, and millisecond anneals. Together, these two simulation platforms provide actionable design rules and quantitative benchmarks that enable cost-effective nanolithography and high-precision dopant engineering, thereby advancing the manufacturability of next-generation CMOS technology.