The growing complexity and heterogeneity of modern application-specific integrated circuits has made hardware design methodologies a limiting factor in the construction of future computing systems. This work aims to alleviate some of these design challenges by embedding productive hardware modeling and design constructs in general-purpose, high-level languages such as Python. Leveraging Python-based embedded domain-specific languages (DSLs) can considerably improve designer productivity over traditional design flows based on hardware-description languages (HDLs) and C++, however, these productivity benefits can be severely impacted by the poor execution performance of Python simulations. To address these performance issues, this work combines Python-based embedded-DSLs with just-in-time (JIT) optimization strategies to generate high-performance simulators that significantly reduce this performance-productivity gap. This thesis discusses two frameworks I have constructed that use this novel design approach: PyMTL, a Python-based, concurrent-structural modeling framework for vertically integrated hardware design, and Pydgin, a framework for generating high-performance, just-in-time optimizing instruction set simulators from high-level architecture descriptions.