Driven by the improvements on performance and cost, new generations of complementary metal oxide semiconductor (CMOS) memory devices such as SRAM, DRAM, and Flash have been aggressively scaled down to the deca-nanometer regime and beyond. Continued advancement of the CMOS technologies reduces the feature size and pitch and lowers the supply voltage to constrain power consumption. Cells and systems based on these devices are becoming more susceptible to process variations and transistor mismatches, causing various scaling challenges. On the other hand, researchers have recently demonstrated that inherent manufacturing variations can be exploited to authenticate an IC instance or generate unique secrets for each chip. This primitive is named physical unclonable functions (PUFs). In this work, we first study the impact of process variations on the 22nm prototype SRAM performance and stability caused by random dopant fluctuation (RDF), which is one of the dominant variation sources for sub-100nm devices. Hybrid SRAM-DRAM with cross capacitors is then designed and investigated for multi-bit storage, mismatch tolerance, and disturb stabilization capabilities, which help mitigate the severe scaling challenges in density, performance and stability. Finally, variation sources behind Flash PUF (FPUF) are decomposed and characterized to provide theoretical foundations for better implementation and utilization in security applications. Algorithms to improve the FPUF consistency and entropy are also discussed.