This thesis explores techniques for measuring, monitoring and maintaining timing at small and large scales. At small scales, timing non-idealities of clock signals is of interest. As clock speeds become higher and higher in modern circuits, non-idealities such as clock duty-cycle, clock skew and jitter become proportionally large. Therefore, on-chip characterization of the clock using low power is important. A stochastic technique for on-chip measurement of such non-idealities is introduced. The technique uses a simple noisy oscillator to perform random sampling, allows easy integration in a CMOS process and is a promising alternative to direct measurement. Theoretical analysis proving the accuracy and robustness of the technique is presented. An implementation in CMOS 65nm process, occupying an active area of 0.015 mm2 and consuming 0.89 mW, achieves a root mean square error of 0.1 ps and 0.31 ps in externally referenced and self-referenced jitter measurements respectively. To the best of our knowledge, the stochastic technique is the only fully on-chip jitter measurement technique that does not require post processing to obtain the jitter amplitude. At large scales, this work explores a technique to achieve and maintain low-power synchronization of long-range peer-to-peer (P2P) RF system. Once synchronized, radio nodes can achieve significant power savings by turning off the RF front-end most of the time. Such aggressive duty-cycling allows battery operated radio to directly communicate over long range, enabling a variety of applications, such as IoT devices that do not strain the existing infrastructure and communication in natural disaster scenarios where infrastructure is unavailable. Existing synchronization techniques for narrowband radio are not scalable to large number of nodes and are often asymmetric (e.g. they require one central node that consumes high power). To solve this problem of scalable, long-range, P2P narrowband radio synchronization, a low-power signal-processor utilizing the pulse coupled oscillator (PCO) scheme for low-latency detection of syncword for aggressive duty-cycling is presented. The signal processor is insensitive to phase and frequency mismatch and compatible with commercial RF front ends. It consumes 5.1 uW in 0.01% duty-cycled mode while detecting a 63-bit syncword at 1.25 Mbps with BER=10-3 at SNR=18.4dB.