Power consumption in digital systems will be the bottleneck of future high performance and mobile computing. For the past four decades, the wireline communication bandwidth, the number of packaging pins, and transistor density have grown exponentially. Meanwhile, the power consumption has also grown at the same rate when the conventional scaling rule is applied. The ratio of data throughput rate over system power consumption is the figure of merit which has to be addressed for future designs on top of geometrical scaling. Although continuing advancement on the complementary metal oxide semiconductor (CMOS) technologies reduces the device feature size, pitch, and supply voltage simultaneously as well as enables higher transistor count and operation frequency for larger data and link bandwidth, the frequency dependent loss becomes a serious issue for energy-efficient system. The low-power and high-speed design has been the backbone to develop the nextgeneration electronic device, which requires new nonlinear concepts on the CMOS roadmap. In this dissertation, a novel switch is proposed and implemented using single-layer graphene as the channel material to provide higher carrier mobility, bandgap modulation and efficient band-to-band tunneling. System implementation and process integration in the frontend space lithography and backend thin films are proposed and verified. On the system point of view, the passive transmission equalization by nonlinear transmission line (NLTL) is used as a receiver front-end to reduce the inter-symbol interference (ISI) and suppress the phase noise (PN) without adding power budget. The device structure tradeoffs and system design optimization are also discussed.