2026-09-18T23:15:11Zhttps://ecommons.cornell.edu/server/oai/requestoai:ecommons.cornell.edu:1813/478782026-05-15T19:47:59Zcom_1813_35col_1813_47
Wang, Yao
Suh, Gookwon Edward
Myers, Andrew C.
Batten, Christopher
2017-04-04T20:28:22Z
2017-04-04T20:28:22Z
2017-01-30
ProQuest Submission ID: 10146
ProQuest Publication ID: 10253735
https://hdl.handle.net/1813/47878
https://doi.org/10.7298/X49K487W
9906125
Modern computing systems are becoming increasingly vulnerable to timing
channel attacks that leak confidential information through the timing of
microarchitectural events. Many timing channel attacks are caused
by the interference between different programs in the shared resources
of a multi-core processor. For example, an attacker program's cache lines
can be evicted by a victim program, which allows the attacker to infer
secret information about the victim. Timing channel attacks pose serious
threats to contemporary computing systems because they can bypass
traditional defense mechanisms such as access control. Previous
studies have even demonstrated a practical timing channel attack to recover
the keystrokes of a user in the commercial Amazon EC2 cloud.
In this thesis, we explored new timing channel attacks and developed timing
channel protection schemes for some of the hardware resources in a multi-core
processor. Specifically, we discovered new timing channel attacks in the
shared on-chip networks and memory controllers. We proposed multiple
protection mechanisms for on-chip networks, caches and memory controllers.
Our protection schemes cover three high-level approaches: bi-directional
protections, uni-directional protections and protections that trade off
security for performance. We evaluate our protection schemes and
show that the proposed schemes are effective against timing channel attacks
while achieving performance improvements over previous protection schemes.
Finally, we implemented some of the protection mechanisms in RTL and used
SecVerilog to verify the information flow control in hardware. The results
show that the protection mechanisms indeed remove timing channels at the
gate level.
en_US
Computer engineering
Computer science
Computer Architecture
Memory Controller
Security
SecVerilog
Timing Channel
cache
Efficient and Verifiable Timing Channel Protection for Multi-Core Processors
dissertation or thesis
application/pdf
Electrical and Computer Engineering
Cornell University
Doctor of Philosophy
Ph. D., Electrical and Computer Engineering
https://hdl.handle.net/1813/59810
Publication
Cornell Theses and Dissertations
Wang, Yao
5893a6ea-7af3-41d7-abc6-04bcd26ab5df
open.access
open.access
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<Abstract>Modern computing systems are becoming increasingly vulnerable to timing
channel attacks that leak confidential information through the timing of
microarchitectural events. Many timing channel attacks are caused
by the interference between different programs in the shared resources
of a multi-core processor. For example, an attacker program's cache lines
can be evicted by a victim program, which allows the attacker to infer
secret information about the victim. Timing channel attacks pose serious
threats to contemporary computing systems because they can bypass
traditional defense mechanisms such as access control. Previous
studies have even demonstrated a practical timing channel attack to recover
the keystrokes of a user in the commercial Amazon EC2 cloud.
In this thesis, we explored new timing channel attacks and developed timing
channel protection schemes for some of the hardware resources in a multi-core
processor. Specifically, we discovered new timing channel attacks in the
shared on-chip networks and memory controllers. We proposed multiple
protection mechanisms for on-chip networks, caches and memory controllers.
Our protection schemes cover three high-level approaches: bi-directional
protections, uni-directional protections and protections that trade off
security for performance. We evaluate our protection schemes and
show that the proposed schemes are effective against timing channel attacks
while achieving performance improvements over previous protection schemes.
Finally, we implemented some of the protection mechanisms in RTL and used
SecVerilog to verify the information flow control in hardware. The results
show that the protection mechanisms indeed remove timing channels at the
gate level.</Abstract>
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