PROCESS INVARIANT CIRCUIT TECHNIQUES FOR RELIABLE MIXED SIGNAL SYSTEMS A Dissertation Presented to the Faculty of the Graduate School of Cornell University In Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy by Mustansir Yunus Mukadam August 2012 i © 2012 Mustansir Yunus Mukadam ii PROCESS INVARIANT CIRCUIT TECHNIQUES FOR RELIABLE MIXED SIGNAL SYSTEMS Mustansir Yunus Mukadam, Ph D. Cornell University 2012 CMOS scaling has enabled circuit designers to develop a wide variety of fully integrated mixed signal systems by taking advantage of the high switching speeds and lower noise figures offered by these devices. Unfortunately, scaled CMOS increasingly suffer from large variations in expected performance due to defects in manufacturing and fluctuations in environmental conditions. This phenomenon is termed as process variation and it ultimately impacts yield of mixed signal systems. Post fabrication tuning efforts to correct for these effects is an expensive solution and, in some cases, infeasible. This work proposes a variety of circuit techniques to combat variations in standard mixed signal blocks such as low noise amplifiers (LNA), voltage controlled oscillators (VCO), and digital to analog converters (DAC). An on-chip statistical technique, designed in the TSMC 65nm CMOS process, tracks changes in threshold voltage due to variations in process, temperature, and supply voltage, and provides an error correction signal to the LNA. Silicon measurements show that our technique reduces the variation in voltage gain of LNAs by a factor of 3.6. We also demonstrate that this technique can be applied to other amplifiers designed in advanced CMOS processes and demonstrate with a common source amplifier. A switched capacitor based feedback loop, designed in the IBM 90nm CMOS process, generates an error signal based on the drift in the center frequency of VCOs and provides an appropriate correction signal to compensate for the drift. Measured results show a 2.5x reduction in center frequency variation of the VCO. We propose using redundancy in a DAC to tighten the error distribution of DAC elements and improve non-linearity. Measured results of an 8 bit thermometer current steering DAC designed in the TSMC 65nm CMOS process show 38% reduction in non-linearity. Another technique to reduce non-linearity is reordering of elements based on their error distribution. This reduces non-linearity by an additional 30%. Combining both schemes significantly reduces induced non-linearity errors with minimal area and power increase. BIOGRAPHICAL SKETCH Mustansir Yunus Mukadam was born in Mumbai, India in April 1984. He grew up entirely in the United Arab Emirates, in the Middle East, shuttling between Abu Dhabi, Sharjah, and finally, Dubai, where he graduated first in his high school class of 2001. From the extreme heat of Dubai, he moved to the frigid climate of Montreal where he studied Electrical Engineering at McGill University. After graduating from McGill in 2006, Mustansir moved to the boonies in Ithaca, NY in the position of a Graduate Research Assistant in Dr. Apsel’s lab at Cornell University. He started his research with high speed opto-electronic receivers but finally settled on developing process invariant circuit techniques to improve yield and performance of various mixed signal blocks used in wireline and wireless systems. In between all of this, he took a break from the rigors of a PhD to intern as a Mixed Signal designer at PMC-Sierra Inc. in Vancouver, BC, from January 2011 to May 2011. Mustansir finished his PhD in August 2012 and moved to the Bay Area where he will work with the XBOX team at Microsoft in Mountain View. iii ACKNOWLEDGEMENTS This thesis would not have been possible without the contributions, help, and support from the following people. First and foremost, my advisor, Dr. Alyssa Apsel, for her constant support in my work, belief in my ideas, and encouraging inputs and critiques in realizing and polishing the works in this thesis. This work would not have been possible without her. My dissertation committee members, Dr. Ehsan Afshari and Dr. K. Max Zhang, for their guidance and help in various stages of this work. My fellow collaborator, Ishita Mukhopadhyay, was essential for accomplishing the concepts, circuit design, layout, and testing of the work on digital to analog converters, and an excellent lab mate to interact with overall. Without Xiao Wang’s superior testing skills and board designs, we would not have been able to test various aspects of the DAC circuit. Oscar Filho and Xuan Zhang were crucial towards conceptualizing the work done in process invariant low noise amplifier and voltage controlled oscillator designs. I’d also like to thank the various group members I have interacted with over the past six years at Cornell; Rajeev, Bo Sr., Bo Jr., Wacek, Carlos, Tony, Zhongtao, Nick, and Jerry. The support from Cornell NanoSciences and National Sciences Foundation was crucial towards completion of this thesis. Without fabrication runs provided by TSMC, we would not have any results to show. iv My family has always been a pillar of strength and motivation. My mother has provided me with moral support and guidance through each of my struggles during this thesis. Not a day goes by when I don’t miss my dad and his practical advice and sound judgment on all matters of life. My aunt Anjum, uncle Ebrahim, and cousins Sarah and Taher form part of the best family anyone could ever have. Lastly, the time spent at Cornell would not have been enjoyable and memorable without the many friends I made. Krishna, Shantanu, Suresh, and Tanay are the best compadres for daily coffee sessions, random discussions on life, and criticisms of the Indian cricket team. My Monday night trivia team for the entertainment and relief from the PhD. Various members of the Cornell India Association with whom I had the pleasure of organizing too many events to count. A special shout out goes to a ton of other friends I made at Cornell who are way too many to name in this thesis. v TABLE OF CONTENTS Biographical Sketch Acknowledgements List of Figures List of Tables 1. Introduction 1.1: The CMOS Industry 1.2: Scaling in Analog CMOS 1.3: Process Variation 1.4: Goal of the Dissertation 1.5: Organization of the Dissertation 2. Process Variation in CMOS Technology 2.1: Scale of Variations 2.1.1: Inter-die Variations 2.1.2: Intra-die Variations 2.2: Random Dopant Fluctuation vi iii iv xii xviii 1 1 3 5 5 6 7 7 7 8 10 2.3: Line Edge Roughness 2.4: Impact of RDF and LER on Threshold Voltage 2.5: Impact on Integrated Circuits 2.6: Impact of Process Variation on the IC Industry 2.7: Impact of Process Variation on Energy Usage in Industry 14 16 18 23 25 3. Process Compensation of Amplifiers 3.1: Introduction 3.2: Related Work 3.3: Amplifier Variations 3.3.1: Variations in the LNA 3.3.2: Variations in the CSA 3.4: Correction Scheme 3.4.1: Proposed Solution 3.4.2: Temperature Variation 3.4.3: Supply Voltage Variation 3.5: Compensation Circuit Design vii 28 28 30 31 32 34 35 35 38 39 41 3.5.1: First and Second Stage 42 3.5.2: Third Stage 43 3.5.3: Fourth Stage 43 3.5.4: Performance of the Bias Circuit 3.6: Design Example I – 3.2 GHz Low Noise Amplifier 45 46 3.6.1: Measured PVT Results of the LNA 46 3.6.2: Impact on Input Matching, NF, and Linearity of the LNA 49 3.6.3: Yield Analysis and Comparison to Other Work 3.7: Design Example II – Common Source Amplifier 51 52 3.8: Conclusion 54 3.9: Appendix A 54 3.9.1: Amplifier Derivation of transconductance variation in the Low Noise 54 3.10: Appendix B 55 3.10.1: Derivation of gm variation with supply voltage 55 4. Process Compensation of Oscillators viii 59 4.1: Introduction 4.2: System Design Concept 4.3: System Design 4.4: Frequency Correction Unit 4.4.1: Initialization Stage 4.4.2: Comparison Stage 4.4.3: Correction Stage 4.5: Loop Stability 4.6: Accuracy Analysis 4.7: Low Variation Current Source 4.8: Voltage Controlled Oscillator 4.9: System Measurement Results 5. Mismatch Compensation of Digital to Analog Converters 5.1: Current Steering DACs 5.2: Differential Non-Linearity 5.3: Integral Non-Linearity ix 59 60 61 62 63 64 65 66 68 69 70 70 75 75 77 78 5.4: Prior Work in Calibration of Current Steering DACs 5.5: Proposed Solution 5.5.1: Error Analysis of Differential Non Linearity 5.5.2: Error Analysis of Integral Non-Linearity 5.5.3: Redundancy 5.5.4: An 8-bit Redundant Thermometer DAC 5.5.5: Practical Realization of a Redundant N-bit DAC 5.5.6: Reordering 5.5.7: Reordering in a 2-Dimensional DAC 5.5.8: Combining both Redundancy and Reordering 5.6: Circuit Implementation and Challenges 5.6.1: First Generation DAC Design 5.6.2: Second Generation DAC Cell Design 5.6.3: Generating the Mean Current 5.6.4: Median Generation 5.6.5: High Resolution Current Comparator 5.6.6: Eliminating Outliers x 79 82 83 84 85 86 89 92 95 97 98 102 105 109 111 112 114 5.6.7: Cost of Calibration on Overall DAC Design 5.7: Conclusion 6. Conclusion 6.1: Conclusion 6.2: Future Work References 114 115 117 117 119 120 xi LIST OF FIGURES Figure 1.1: Edholm's law projecting required bandwidth for various communication systems Figure 1.2: RF transceiver market share versus technology Figure 1.3: Simulated cutoff frequency of NMOS devices of various nominal gate lengths Figure 1.4: NFmin at 2.4 GHz versus gate length Figure 2.1: Scale of variations in an Integrated Circuit Figure 2.2: Oscillation frequency of identical devices with different layouts Figure 2.3: Variation extractor at various levels of the IC fabrication process Figure 2.4: Atomistic simulation of a 50 x 50nm MOSFET Figure 2.5: Scaling trend of Vth variance due to RDF Figure 2.6: Distribution of Vth as a function of the number of dopants for a (a) 35nm device and (b) 13nm device Figure 2.7: Potential distribution at the Si/Si02 interface of two microscopically different MOSFETs Figure 2.8: LER in advanced lithography processes Figure 2.9: Potential distribution of a 200nm x 30nm MOSFET in the presence of LER Figure 2.10: Vth fluctuations associated with LER as a function of its amplitude Figure 2.11: Vth deviation in the presence of RDF, LER, and both effects 2 3 4 4 7 8 9 11 12 13 14 15 15 16 17 xii Figure 2.12: Normalized Vth variation of a 65nm MOSFET Figure 2.13: Normalized leakage current distribution of a 65nm MOSFET Figure 2.14: Fault statistics of a 32 K SRAM in 45nm technology Figure 2.15: Measured leakage power and frequency for 62 dies Figure 2.16: Distribution of the performance parameters of a narrowband LNA at 2.4 GHz Figure 2.17: Impact of parameter variations on RF performance Figure 2.18: Measured receiver gain and noise figure over fast, typical, and slow process corners Figure 2.19: Measured receiver gain and noise figure over operating temperature (left) and supply voltage (right) Figure 2.20: System level illustration of a 16-QAM RF Receiver Figure 2.21: Yield of ICs and its impact on profit Figure 2.22: Iterative performance calibration in which knobs are tuned until an IC is healed Figure 2.23: Relative cost to manufacture and test a transistor Figure 2.24: Energy use per cm2 of wafer area Figure 3.1: Circuit diagram of the inductive cascode LNA Figure 3.2: Circuit diagram of the common source amplifier Figure 3.3: Circuit diagram of the compensated LNA 18 18 19 19 20 21 22 22 23 23 24 25 25 32 34 36 xiii Figure 3.4: Circuit diagram of the bias circuit Figure 3.5: gm of input transistors M1 and M2 in the compensated amplifier Figure 3.6(a): Histogram of voltage gain of the uncompensated LNA over two wafer runs Figure 3.6 (b): Histogram of voltage gain of the compensated LNA over two wafer runs Figure 3.7: Gain of uncompensated and compensated LNA with supply voltage variations Figure 3.8: Gain of uncompensated and compensated LNA with temperature variation Figure 3.9: Die photo of compensated LNA Figure 3.10(a): Measured NF of the LNA without compensation Figure 3.10(b): Measured NF of the LNA with compensation Figure 3.11(a): Histogram of voltage gain of the uncompensated CSA over two wafer runs Figure 3.11(b): Histogram of voltage gain of the compensated LNA over two wafer runs Figure 4.1: System Diagram of the General Compensation Loop Figure 4.2: Switched Capacitor based VCO tuning circuitry Figure 4.3: Discrete time switched capacitor integrator Figure 4.4: Timing waveform controlling switches in the frequency sensor Figure 4.5: Initialization Stage Figure 4.6: Comparison Stage 42 45 47 47 48 48 49 50 50 53 53 60 61 62 63 64 64 xiv Figure 4.7: Correction Stage Figure 4.8: Low Variation Addition Based Current Source Figure 4.9 (a): Histogram of uncompensated VCO Figure 4.9 (b): Histogram of compensated VCO Figure 4.10: Temperature drift of baseline oscillator and oscillator in Switched Capacitor loop Figure 4.11: Convergence behavior of VCO compensation loop Figure 4.12: Die photo of Switched Capacitor based VCO Compensation Figure 5.1: Calibration DAC used in a Direct Conversion receiver architecture Figure 5.2: Offset compensation in comparators using a calibration DAC Figure 5.3: DNL error in DACs Figure 5.4: INL error in DACs Figure 5.5: Introducing redundancies in current sources to reduce errors Figure 5.6: Error Variance of current sources in an 8 bit DAC design with and without redundancy. Figure 5.7: Worst case DNL value with and without redundancy Figure 5.8: DNL Variance with and without redundancy Figure 5.9: Illustration of a 2-Dimensional current steering DAC 65 69 71 71 72 73 73 76 76 78 79 86 87 88 88 89 xv Figure 5.10: Variance of the DNL Figure 5.11: 5000 Monte Carlo runs plotting DNL Figure 5.12: Reducing INL error by alternatively switching Figure 5.13: Worst case INL for 1-dimensional DAC with element reordering Figure 5.14: Variance of INL for each code of the DAC over 5000 Monte Carlo runs Figure 5.15: Worst case INL Figure 5.16: Variance of INL at each code Figure 5.17: 3σ of INLDAC across different current source mismatch Figure 5.18: 3σ of for methods presented in this work Figure 5.19: Positional chart to determine redundant sources Figure 5.20: DAC Cell with SRAM Figure 5.21: 6T SRAM with a transistor to read its contents Figure 5.22: Outlier access Figure 5. 23: Unit Current Cell of thermometer current cell - Generation 1 Figure 5.24: Chip micrograph of the DAC designed in the TSMC 65nm process Figure 5.25: Measured results of DNL of the 8-bit thermometer current steering DAC. Figure 5.26: Measured results for INL of 8-bit thermometer current steering DAC. xvi 91 92 93 94 95 96 96 97 98 99 100 100 101 103 103 104 105 Figure 5.27: Unit cell designed for the second generation of the DAC 106 Figure 5.28(a): Scenario 1: Cell under consideration is the highest accessed cell 107 Figure 5.28 (b): Scenario 2: Cell under consideration occurs (red) before highest accessed cell 107 Figure 5.29: DAC DNL for various sizes of current contributing PMOS 108 Figure 5.30: Plot of median confidence for various errors 111 Figure 5.31: Median Generation using a successive approximation approach 112 Figure 5.32: High Precision Current Comparator 113 Figure 5.33: Sampling (fast) and averaging (slow) clocks used in comparison 113 Figure 5.34: Time-to-Digital converter 114 Figure 5.35: DNL reduction taking area occupied by the calibration circuitry into account 115 xvii LIST OF TABLES Table 3.1: Design Parameters of the Bias Circuit Table 3.2: Performance of the Bias Circuits under Process Corners Table 3.3: Comparison with Other Work Table 3.4: Summary of Measurement Results Table 5.1: Truth Table for Priority Encoder Scheme 44 45 51 53 101 xviii CHAPTER 1 The CMOS Industry INTRODUCTION CMOS transistors have transformed the world in which we live. From portable electronics such as cellphones and tablets, to control systems in automobiles and transport systems, and complex communication systems including satellites orbiting our earth, transistors form an integral part of our daily lives. The semiconductor industry, virtually dominated by CMOS, is a $300 billion revenue market, growing at a rate of 30% annually [1] . This astronomical growth is partly due to CMOS technology continuing to follow Moore’s Law. Moore’s law, proposed by Gordon Moore in 1956, is an economic indicator whereby the number of transistors placed inexpensively in an integrated circuit doubles roughly every 18 months [2]. This has been made possible by continuing to shrink the size of the CMOS transistor during the same interval. Scaling CMOS processes are also beneficial for designing high performance analog and RF systems. Over the past decade we have achieved cellular data rates that match and even exceed the bandwidth obtained from the highest Ethernet speeds of the mid noghties. This exponential increase in annual data rates has been termed the Edholm’s law of bandwidth, in honor of Phil Edmond, chief technology officer of the now defunct Nortel Networks [3] and it closely follows Moore’s law. Seen in Figure 1.1, the three telecommunication categories – wireline, nomadic, and wireless – follow similar trends with data rates increasing on exponential curves and wireless applications following their wireline counterparts with a constant time lag. This is not too surprising, however, since all technologies rely on the same core technology of the radio with the 1 wireless devices requiring faster and more powerful radio transceivers with the introduction of newer communication protocols. Figure 1.1: Edholm's law projecting required bandwidth for various communication systems [4] Researchers over the last ten years have focused on the ultimate goal of integrating analog and RF CMOS devices with the digital baseband on the same chip [5] [6] [7] [8] to take advantage of the inexpensive yet powerful digital logic, fast switching, and higher capacitance density obtained from digital CMOS processes. The use of RF devices in the analog front end would ultimately replace the high performing, but more expensive, silicon germanium (SiGe) and BiCMOS technologies previously used in the RF front ends with the aim of full system-on-achip integration and reduced costs and overheads associated with off-chip integration. Indeed, the increasing market penetration of analog and RF CMOS has in the cellphone market, shown in Figure 1.2, confirms a continuously growing trend. 2 Figure. 1.2: RF transceiver market share versus technology [9] Scaling in Analog CMOS Based on the chosen transistor widths for scaled CMOS, the scaling rules in (1) apply for RF CMOS performance [10]. ⁄⁄ (4.1) λ is the technology scaling factor. (1.1) indicates that, as transistor feature sizes shrink, their cutoff frequency fT increases. Woerlee et. al. present the fT of nominal gate length NMOS devices as a function of its drain current in [11] presented here in Figure 1.3. It is evident that, for both low and high drain currents, fT increases with down scaling, confirming the high potential of CMOS for RF applications at gigahertz frequencies 3 Figure 1. 3: Simulated cutoff frequency of NMOS devices of various nominal gate lengths [56] The minimum noise figure of an FET, as determined by Fukui in [12] and expressed in (1.2) states that NFmin scales with λ. This is verified in Figure 1.4. This decrease is mainly due to the increase in fT. (4.2) Figure 1.4: NFmin at 2.4 GHz versus gate length. Solid dots are obtained from fabricated devices in a standard 0.18-µm process [13] . 4 Process Variation Although CMOS scaling is advantageous in terms of the increase in fT and decrease in NF, the devices are more susceptible to increasing shifts in performance from their nominal specifications, termed process variations. Process variation is a naturally occurring variation in the transistor’s physical properties (length, oxide thickness, etc.) due to defects in manufacturing. It is a continuous theme in the history of semiconductor manufacturing but is becoming more and more prominent as devices scale and variation becomes a larger percentage of critical dimensions. Variation in electrical properties of CMOS transistors ultimately translate to variation in circuit performance such as amplifier gain, signal delay, and oscillation of center frequency. As a result, process variation is a detriment to achieving robust integrated circuit systems in sub-micron CMOS, with the International Technology Roadmap for Semiconductors highlighting variation as a key bottleneck in the design of systems with high yield [14]. Goal of the Dissertation The goal of this dissertation is to develop tools to combat variations in performance of critical analog and RF blocks used in a wide variety of mixed signal applications. The techniques developed are on-chip circuit solutions which occupy a small area footprint and consume little power while providing significant reduction in circuit performance where degradation in performance is measured either as deviation from the nominally designed specification or from difference in behavior of identically laid out components. In order to overcome process variation, a self-calibrating, a statistical feedback loop is designed for a low-noise-amplifier (LNA) which measures changes in threshold voltage due to variations in process, temperature, and supply voltage, and generates a control signal to correct for 5 deviation in LNA performance. This technique is also extended to a common source amplifier to demonstrate adaptability to other types of amplifiers. To correct for variation in the center frequency of voltage controlled oscillators (VCO), a switched capacitor feedback loop is designed to track frequency error and generate control signals to mitigate the drift in center frequency. To minimize degradation in performance due to component mismatch, a calibration technique using redundancy in identically laid out elements is employed on a thermometer current steering digital-to-analog converter. With a small increase in the number of elements, 40% improvement in linearity is experimentally demonstrated. Reordering of elements based on their distribution is used to reduce integral non-linearity errors with minimal hardware penalty. We also propose combining both redundancy and reordering to further improve DAC linearity with low area and power penalty. Organization of the Dissertation This dissertation consists of six chapters. Chapter 2 will discuss the sources and scale of process variation and its overall impact on mixed signal circuit systems and the semiconductor industry. In Chapter 3, we will present a technique to overcome amplifier gain variations due to variations in process, supply voltage, and temperature in low noise amplifiers and common source amplifiers. In Chapter 4, we will discuss a scheme to reduce the spread in center frequency of voltage controlled oscillators. In Chapter 5, we will present an approach using redundancy in identically laid out current sources in a thermometer current steering DAC to reduce nonlinearity errors. Finally, in Chapter 6, we will summarize the conclusions of this research and propose some future research directions. 6 CHAPTER 2 PROCESS VARIATION IN CMOS TECHNOLOGY Scale of variations Process variation can generally be divided into two categories – inter-die variations and intra-die variations [1] [15] . Figure 2.1: Scale of variations in an Integrated Circuit [16] Inter die variations Inter die variations occur from one die to the next. This means that the same device has different electrical characteristics and performance among different dies of a wafer, from wafer to wafer, and from wafer lot to lot. Lot-to-lot and wafer-to-wafer variations are caused by parameters such as process temperature, equipment properties, wafer polishing and placement. They affect every 7 device on the chip equally, and are generally deterministic, or systematic in nature [17] . Withinwafer variations can be attributed to issues such as resist thickness across dies [18]. Intra-die variations Intra-die variations are variations in device features present within a single chip. This means that seemingly identical devices have varied characteristics based on their location on the same chip. Systematic variations in devices within the same die have a known quantitative relationship to a source and can be modeled. For example, lithography and etching errors can easily be quantified. These variations have a strong spatial correlation and can be characterized by placing test structures at several locations on chip [19] . Layout dependent errors, which refer to two devices having different characteristics due to differences in layout, can be easily modeled in the design. Figure 2.2: Oscillation frequency of identical devices with different layouts In general, process variation at any scale of IC design can be decomposed with an additive model, shown in Figure 2.3, where estimates of variation at each level that match empirical observations are termed systematic, with residuals from one estimator becoming the input to the next level. The sum of all the estimates becomes systematic sources of variation, which can be 8 accounted for non-idealities at different levels in the fabrication process. Systematic sources are an indicator of how far away the performance of the CMOS system is from the nominally designed value and they can be simulated with process corners at set standard deviations from the mean value of an electrical parameter [20] . et al.: ANALYSIS AND DECOMPOSITION OF SPATIAL VARIATION 25 ion as one moves across a wafer. For instance, die the edge of the wafer tend to have quite different ion profiles compared to die near the center of the . New methods for capturing these interaction terms are uced in Section V. Methods for analysis of the residuals ning after systematic components have been removed resented in Section VI. This section further provides a s for the comparison and evaluation of the effectiveness decomposition algorithms in Sections III through V. In on to presenting the methods used to factor variation, we lso demonstrate the methodology on two datasets. The s an artificial dataset created to test the efficacy of each estimators as they are presented in Sections III through description of this dataset is provided in Appendix A. econd example uses data collected from an experiment ned to investigate interlevel dielectric thickness (ILD) ion in chemical-mechanical polishing (CMP) processes. dataset and analysis results are described in Section VII. y, concluding remarks and directions for future work are ded in Section VIII. II. VARIATION CLASSIFICATION AND DEFINITION iation in semiconductor manufacturing appears largely r different scales in time and space: lot-to-lot, wafer-to- , within-wafer, and intra-die. Lot-to-lot variation is the ncy of the lot mean of a device or process parameter Fig. 1. Variation decomposition method flow diagram. the mean of channel length computed over the entire o vary from one monitored using lot to the statistical next. Lot-to-lot variation process cFonitgroul raend2m.3ay: VbiesariwaatBfieeorc-nauasneedxtthdreiae-cplehtvoyesrliscaaaltresvoauvrercrieyos udoisfffelsrepevanttie,allist voaisrfiacttrihoitniecaaIl tCththafetabrication process ensated for using run by run or other feedback control methods be available for the separation and analysis of varia- aches, e.g. [10]. Wafer-to-wafer variation may be either tion components. Equipment and process-related issues can orgaelnoerraslplyatciaalusinednbaytudrTeri.fhtTieenmppfrooincraealsslweaqbfueoirp-xtmo-ewnrteafopeprreervaastrieioann- ts thtehnebepoidretnitiofined oanfd raedsdirdesuseadlsvialepfrtoceosvs eorptiamnizdatiotnhose and control, and pattern dependencies can be minimized by are termed as random one wafer to the next. This variation is increasing in judicious circuit design practices. tance as single-wafer sporoucerscsiensg eoqfuipvmaernitaetxipoannd.s RinandoFimg. 1ssohouwrscea sfloowfdivagarramiatfoior tnheagreenerdaludeecotmoposstiatitoinstical uncertainty in process Spatial wafer-to-wafer variation may also result from algorithm we have developed. A hierarchical model is assumed eal process equipment, e.g. due to different positions of in which the residuals (the output of the previous estimator s in a boat during a bcatochndfuirtniaocenssteaps. critical lengmthinsusoiftsCinMputO) fSromdeonveicesetismsatcoar lbeec[o2m1e ]theainnpdutatorethae n indicator of how different fer-level variation is generally caused by additional next estimator. There are three main estimators depicted in ment nonuniformity and other physical effects such as al gradients and loaditnhgephpeenormfoenram. Taynpcicealloy,fwtawfeor- idFtheiegn.wt1ia:cfetahr–leldywieaidfneetre-srleaivcgteinloneesdtteimrmdateoevsr,tiimtchaeetsodri.aeD-rleeevt,aeiloleedrstdtimehsaectroimpr,tiaoinsndsmatch between two identical variation is low frequency and smooth, and neighboring of these estimators are presented in Sections III, IV, and V, are likely to be highly correlated with each other. Also, -level variation oftenCeMxhiObitSs sdymevmiectreicsa.l Eprfofpeerctitess as radial (or “bull’s eye”) patterns or slanted planes. surteecrsmphesc—ativstheelvy.apTorryhteiionnfignoalfnbuthomex bivnaerFriaigtoi.ofn1 drtehoparptesaiesnnttlsesftth(edovureeersidatunoadl assumed to be purely random in nature. its discrete nature in scaled a-die ction variation with the ipsroofcteesnps.craoKucseeyedsebsxyeamlsa)py,loeustgaiannctdleutodpeooxgpraiatdtpeheryn thicGkenneeraslsly, sapenadkingc,hthaenvnaerialtiolnendegctohmpovsaitrioinatailogonristhmlead can be expressed in the framework of an additive model. An to differences between ization in chemical mechanical polishing [11], and crit- excellent discussion of generalized additive models, of which newidth dimension variation in channel length or metal we use a special case, can be found in [14] and [15]. Using an [12], [13]. Intra-die variation has only recently received additive model allows the parameter of interest to be expressed ciable attention, in part due to the need for a large amount as the sum of several contributions, each with their own tistically meaningful data, and the prevailing belief that distributions or dependencies, such as die-level components die variation is inconsequential compared to lot-to-lot, -to-wafer, and within-wafer variation. Several studies [9], level , wafer-level components components9 , and die-cross wafer [13] have shown that this is not the case and that intra- ariation is often much larger or comparable to the other ional sources. where (1) identical devices, which can only be estimated with empirical models. We discuss these effects in the following section. Random Dopant Fluctuation As feature sizes shrink, statistical variation in the number and placement of dopant atoms in the MOSFETs leads to significantly random fluctuations in transistor performance such as deviations in threshold voltage (Vth), drive current mismatch, and so on. Even if fluctuations due to lithographic dimensions and layer thicknesses can be well controlled, random fluctuation of the small number of dopant atoms and their microscopic arrangement in the channel will still lead to significant variations in the transistor’s electrical parameters. This phenomenon is known as random dopant fluctuation (RDF), shown in Figure 2.4, and is considered as one of the significant contributors to device mismatch of identical devices and overall transistor variation and increases with device scaling as the average number of dopant atoms decreases. 10 Figure 2.4: Atomistic simulation of a 50 x 50nm MOSFET. (a) Potential distribution with position of dopants (b) One equi-concentration contour [22] For example, the dopant concentration in the 65nm process is 1018 atoms/cm3 [23] . For a channel of minimum size ( = 60 nm), and width of twice the channel length, the average number of dopant atoms is 100. The dopants typically follow a Poisson distribution [24] with a standard deviation of the square root of the mean number of dopants. In our example, this translates to a 10% variation in the number of dopant atoms, which is a large uncertainty in dopant atoms for sub-micron devices. Since the threshold voltage is a function of the number of dopant atoms, this translates to significant Vth fluctuation, which affects circuit operation. Empirically, it has been shown by Asenov, et. al. in [25] hat the standard deviation of the MOSFET, shown in (2.1) is 11 proportional to the doping concentration and inversely proportional to the transistor’s dimensions. √ (2.1) As devices scale, it is expected that σVth due to RDF will increase. This effect has been captured by Ye, et. al. in Figure 2.5. We can see that the variation in threshold voltage is exacerbated at smaller device dimensions, indicating increased device variation due to RDF for advanced CMOS processes. Figure 2.5: Scaling trend of Vth variance due to RDF [26] Figure 2.6 also shows the distribution of Vth for two devices with different channel lengths as a function of the number of dopant atoms. We notice the increasing mean and standard deviation for the 13nm device, highlighting the adverse effects RDF will have on scaled devices. 12 Figure 2.6: Distribution of Vth as a function of the number of dopants for a (a) 35nm device and (b) 13nm device [27] As mentioned earlier, both the number and the placement of dopants in the channel affects the transistor’s performance. Shown in Figure 2.7, for two MOSFETs with the same number of dopant atoms ( = 170), device (a) has more atoms closer to the channel surface than (b), translating to higher Vth for (a). This discrepancy in Vth for two seemingly identical devices is also due to RDF. 13 Figure 2.7: Potential distribution at the Si/Si02 interface of two microscopically different MOSFETs, both with 170 dopant atoms. (a) has Vth = 0.78V. (b) has Vth = 0.56V [27] Line Edge Roughness Another effect that contributes to variations in threshold voltage is line-edge roughness (LER), which is the distortion of gate shape along the channel width. This variation is mainly due to the gate-etch process. LER is a big concern in short channel transistors since its variance does not scale with technology, therefore it plays a bigger role in Vth variation in scaled CMOS processes [28] . 14 Figure 2.8: LER in advanced lithography processes. The inset shows LER found in sub-100nm ebeam generated lines [29] In Figure 2.8 we can see that LER remains on the order of 5nm, independent of the type of lithography and channel length. This translates to a variation in potential distribution in the scaled device, shown by Reid, et. al. in Figure 2.9. Figure 2.9: Potential distribution of a 200nm x 30nm MOSFET in the presence of LER [27] 15 Similar to RDF, random LER introduces Vth variations in MOSFETs, its effect enhanced for advanced CMOS devices, as shown in Figure 2.10. Figure 2.10: Vth fluctuations associated with LER as a function of its amplitude [29] The standard deviation of Vth due to LER depends on the standard deviation of the RMS value of LER, as shown by Ye, et. al. in [26] , presented here in (2.2) ⁄ (2.2) WC is the correlation length of LER, C2 is a technology dependent coefficient, l’ is the length of DIBL effect. Further work has been done by Asenov, et. al. in [30] to accurately model process parameters which contribute to LER. Impact of RDF and LER on Threshold Voltage The discussion presented above confirms that continuous scaling exacerbates both RDF and LER effects. With continuous scaling, the number of dopant atoms in the channel reduces, making 16 RDF more significant. As gate lengths continue to shrink, they approach the 3σ value of LER, dramatically increasing device sensitivity to LER effects. These effects modeled together impact threshold voltage as follows: (2.3) Graphically, this is represented in Figure 2.11. It is evident that the combined effect of RDF and LER increases the standard deviation of threshold voltage exponentially as device dimensions scale. Figure 2.11: Vth deviation in the presence of RDF, LER, and both effects [26] The impact this total variation on Vth has on transistor performance is evident in Fig. 16 where the Vth fluctuations for a MOSFET designed in the 65nm process exceed 15%. The combined effect of RDF and LER also impacts normalized leakage current, as shown in Figure 2.12. 17 Figure 2.12: Normalized Vth variation of a 65nm MOSFET [31] Figure 2.13: Normalized leakage current distribution of a 65nm MOSFET [31] Impact on integrated circuits Process variations of CMOS devices can be represented by a continuous probability distribution, empirical data, or a combination of both, where the total variation, P, can be expressed as a function of its known distributions, as follows: (2.4) 18 Agarwal, et. al. show, in [32] , how a 30mV deviation in threshold voltage results in a low yield of 33.4% in an SRAM array designed in a 45nm CMOS process. Figure 2.14: Fault statistics of a 32 K SRAM in 45nm technology Tschanz, et. al. demonstrate in [33] how both inter-die and within-die variation affects both the normalized frequency and leakage power of 62 testchips in the 150nm CMOS process. Figure 2.15: Measured leakage power and frequency for 62 dies Variation in frequency leads speed binning to qualitatively sort the working ICs based on the frequency of operation. High frequency ICs correspond to higher price points compared to 19 lower-frequency counterparts [34] . Since there is a larger spread in frequency due to variations, this affects yield and profit margins of IC manufacturers. Process variation is also detrimental to the performance of RF CMOS applications. Figure 2.16 depicts the distribution of an LNA’s performance metrics obtained by Nieuwoudt et. al. in [35] . Both the input and output impedance exhibit a skewed distribution from the mean and the gain and power consumption show a 3σ variation of 30%. Extreme variation in gain and other metrics of the LNA can significantly reduce yield of RF front-ends to as low as 11% [36]. Figure 2.16: Distribution of the performance parameters of a narrowband LNA at 2.4 GHz [35] Figure 2.17 shows the impact of process variation on RF figures of merit such as fT, fmax, and Gmax for five different CMOS technologies. We can notice that the impact of parameter variations on 70nm CMOS is almost double to that of the 250nm technology node. fT suffers the most from process variation because it directly depends on CMOS parameters most affected by 20 process variations. fmax and Gmax depend on parasitics as well which is why their variation is lower. We still observe over 30% variation in Gmax, which directly translates to gain variations of RF circuits. This leads to a lot of overdesign in RF CMOS circuits to increase their tolerances to parametric variations and maintain a higher system yield. Figure 2.17: Impact of parameter variations on RF performance [37] Previously mentioned Vth variations in sub-micron CMOS transistors significantly impact the transconductance of various amplifier blocks in the RF receiver chain, and hence the power gain and noise figure of the entire receiver. RF performance is not only impacted by variations due to process parameters. An integrated circuit has to work under a wide variety of dynamic environmental conditions which leads to prominent drifts in temperature across the chip and fluctuations in supply voltage to various circuit blocks in the RF system. A transceiver designed in 65nm CMOS by Tomkins, et. al. in [38] demonstrates how measured receiver gain and noise figure vary significantly across these three effects. 21 Figure 2.18: Measured receiver gain and noise figure over fast, typical, and slow process corners [38] Figure 2.19: Measured receiver gain and noise figure over operating temperature (left) and supply voltage (right) [38] To further study the impact variation of certain components in an RF transceiver chain has on the overall system performance, we simulated a 16-QAM receiver, shown in Figure 2.20, with measured performance of the low noise amplifier and voltage controlled oscillator designed in the TSMC 65nm CMOS process. Applying as little as 5% variation in the gain of the LNA and 5% variation in the center frequency of the VCO, we observed that the BER of the receiver degrades by a factor of 10. This confirms that variation in critical analog components severely 22 affects sensitivity and linearity performance of typical RF receivers, degrades yield, and increases overall manufacturing costs. Mixer LNA VCO Filter IF Amp 16-QAM Demod. BERT Figure 2.20: System level illustration of a 16-QAM RF Receiver Impact of Process Variation on the IC Industry Ultimately, loss of yield translates directly to loss of profits for IC manufacturers, as indicated in Figure 2.21. Figure 2.21: Yield of ICs and its impact on profit To increase yield of integrated circuits, the “bad” ICs, i.e. the ones whose performance is adversely affected by variations in process, need to be extensively tested and fine-tuned using expensive analog and RF automated test equipment (ATE) to recover yield. This can be a very 23 cost and time insensitive process, increasing exponentially with the number of tunable knobs required to be tweaked to “heal” the currently failing IC. Figure 2.22: Iterative performance calibration in which knobs are tuned until an IC is healed [39] As a result, even though the cost of manufacturing a transistor is rapidly declining – as shown in Figure 2.23 – increasing variation in semiconductor devices is causing the cost to test a transistor to steadily increase, affecting overall cost of manufacturing an IC. Testing an IC accounts for 4050% of the total cost to manufacture an IC and this number is projected to rise by as much as 75% within the next few years [40] . 24 Figure 2.23: Relative cost to manufacture and test a transistor Impact of Process Variation on Energy Usage in Industry Living with the growing concern of finding ways to minimize environmental impact in human actions, it is relevant to talk about the energy usage of the semiconductor industry and the impact yield has on overall energy utilization in manufacture of good ICs [41] . The energy used in manufacturing an IC has remained constant over the last decade at approximately 1.5 kWh/cm2 [42] [43] , despite more transistors being packed in the same area. Figure 2.24: Energy use per cm2 of wafer area [42] 25 This is also due to the cost to manufacture a transistor dropping in every node, as shown in Figure 2.23. The energy density of “working ICs” can be expressed as a function of yield as follows: (2.5) With current first-pass die yields of DRAMs at 50% and RF transceivers at approximately 20%, we can estimate fairly high energy usage in the manufacture of working ICs at 6 kWh and 450 Wh respectively. With RF CMOS accounting for 40% market share of RF transceivers in cellular phones – currently sized at over 1.2 billion [44] – we realize that low initial yields translate to high effective energy costs. For example, a low noise amplifier, which is part of an RF transceiver circuit, can cost up to $0.3/IC and contains, on average, 3 tunable knobs. The overall cost to test the LNA is calculated to be $0.09 [109] for 33 = 27 tests. Total energy consumed per LNA is 45 Wh. If we introduce even one additional knob to overcome process variation, as shown in Figure 2.22, the costs and energy usage will exponentially rise to $0.8/IC and 426 Wh, an increase of 9x! It is obvious that the total energy usage also increases dramatically as we introduce additional knobs to overcome increasing variability in advanced CMOS nodes. The 9x increase seems unreasonable high and rightly so because IC manufacturers would rely on statistical data from batch testing to keep testing costs low. Although obtaining this number was not possible since the information is proprietary, there will still be some increase in costs and energy usage due to additional requirements on testing. 26 If we designed on-chip circuit solutions, we could eliminate a tuning knob, potentially dropping energy usage and costs by a factor of 6. Realistically, however, energy consumption must be looked at by taking the entire system into account. By designing self-healing blocks on the IC itself, if the LNA’s yield goes up by 50%, the overall yield of the RF transceiver increases from 30% to close to 45%. This drops energy used in manufacturing a working RF transceiver to 200 Wh, which is a saving of 100 Wh. With continuous scaling to 22nm and even beyond that, we, as designers, will encounter largely varying device characteristics, making it more challenging to design robust, reliable circuits with high yield. Mitigating process variation is a continuous theme in the semiconductor industry and various circuit solutions have been incorporated on integrated circuits to increase yields. By continuing to design ingenious solutions, process variation will not be an insurmountable barrier to Moore’s law, but simply another challenge to be overcome. 27  CHAPTER 3 Introduction PROCESS COMPENSATION OF AMPLIFIERS Low Noise Amplifiers are the first active block in almost all wireless receiver chains. It is placed immediately, or very close to the receiver antenna and is used to boost the incoming signal power while adding as little noise and distortion as possible. Process variation severely affects performance and yield of LNAs designed in modern processes, especially their voltage gain. According to Friis’ formula for a system of cascaded stages in (3.1), an LNA gain which is lower than the specification it is designed for will not suppress the noise contributions of later stages enough to meet the receiver’s sensitivity requirements. On the other hand, an LNA gain larger than the target value will cause the receiver to fail to meet its intermodulation specifications. It then becomes critical to keep the voltage gain of LNAs stable against process variations in order to maximize the yield of a receiver chain. 28 (3.1) In this chapter, we determine that the variation in threshold voltage of the input transistor is the main contributor to gain variations of LNAs and other standard amplifier configurations where transconductance determines gain. With this in mind, we design and develop a compensation scheme that measures the changes in threshold voltage and generates a bias signal for amplifiers in order to minimize deviations in their voltage gain. We experimentally demonstrate the validity of our method on an inductive degenerated cascade LNA and, to show that our scheme can also be adapted to a variety of such amplifier topologies, we employ it on a common source amplifier which is used as standard gain cells in many mixed signal system applications. Both topologies have been designed in the TSMC 65nm CMOS process. Our work is the first experimental demonstration of successful on-chip PVT compensation of sub-micron amplifiers. Measurement results show that our method is successfully able to lower the variation in voltage gain of the LNA – centered at 3.2 GHz for WiMAX requirements – to 2.2%. This is a 3.7x reduction in the standard deviation of S21 as compared to a baseline, uncompensated LNA, translating to yield improvement of 50%. Our scheme also reduces the variation in voltage gain due to supply voltage and temperature variations by 9.4x and 1.5x respectively. Applying the same technique to a common source amplifier (CSA) shows similar 29 reductions in voltage gain variation. Our scheme occupies a small footprint and consumes very little additional power, making it an attractive low cost solution. Related Work Traditional approaches to detecting and correcting for variations in the gain of amplifiers have relied on using either built-in-self-test (BIST) devices, which either map the peak output signal to a corresponding DC value or introducing additional circuitry which adapts to variations in process. A survey of the state of the art of other LNA compensation schemes in literature shows good examples of these approaches. While BIST based methods can have precise correction, they generally require very high power back-end calibration circuitry, can affect the performance of the amplifier, and are costly in area. Han et. al. devise a calibration scheme in [45] which demonstrates significant reduction in variation of LNA gain but the presence of a DSP and tuning control circuitry makes it very costly in power and area. Jayaraman et. al. in [53] also use peak detectors to maximize S21 gain but off-chip calibration makes it impractical for on-chip, low power solutions. Sen et. al. in [54], use a sensing transistor at the output to control the current in the LNA. However, the large transistor used in the design makes the scheme unsuitable for low supply voltage processes. In [55], Sivonen et. al. identify that the variation in gain of an LNA is a function of its load impedance and, by replacing the load resistor with a parallel combination of different resistance ratios, they demonstrate simulated voltage gain stability over process corners. However, variation of passive elements is reported to be much smaller than that of active elements [56], therefore the major contributor is the variation of the transconductance of the system. Gomez et. al. employ a biasing circuit in [57] to control the variation in the gain of 30 LNAs, but optimally sizing the circuit trades off performance in the presence of both process and temperature variations. This causes the scheme to under-perform with PVT variations. The bias circuit also suffers from stability issues addressed in [58]. Despite the existence of various proposed schemes mentioned above, there has been no experimental demonstration as yet of a precise, low power scheme, which corrects for variations in gain of common amplifier topologies. Our method is based on statistical feedback, where we rely on local match between transistors to track changes in threshold voltage – occurring due to process and temperature variation – from its nominal value. We then generate a correction signal to feed back to the amplifier and correct for changes in gain, without affecting its operation under nominal conditions. Our method also detects and compensates for gain variations caused due to fluctuations in supply voltage. We show that our scheme can be applied to a wide variety of amplifiers, can easily be scaled for advanced CMOS processes, requiring minimal area and power overhead for its implementation. Amplifier Variations In this section, we introduce both amplifier topologies – the CSA and the LNA, which we have used as design examples. We derive the process dependent terms that cause voltage gain variations and the necessary correction that needs to be applied to eliminate gain variations. We then discuss what a compensation scheme must accomplish to overcome variations in such topologies. 31 Variations in the LNA The inductively degenerated cascode LNA, shown in Figure 3.1, is used as the first active block in a variety of wireless Figure 3.1: Circuit diagram of the inductive cascode LNA receiver systems because it provides a good balance between input match, noise figure, and gain. The cascode configuration also provides excellent isolation at the input port. We calculate the resonance frequency of the LNA as , where LS is the source degeneration √( ) inductor, Lg is the gate inductor, and Cgs is the gate-source capacitance of the input transistor. The input tank is able to boost the transconductance of the LNA to [59]: (3.2) 32 Here gm is the small signal transconductance of the input transistor, Rs is the impedance of the input source or the antenna, of the input transistor, and Qin is the quality factor of the input series RLC tank. Using these relations, we can rewrite (3.2) as: √( ) (3.3) where ‘p’ is the state variable denoting the process conditions. To achieve zero variations in the voltage gain of the LNA, we must minimize the total variations seen in (3.3), i.e., we want ΔGm(p) = 0. We note that variation of spiral inductors in sub-micron processes has been shown to have an insignificant impact on the performance of LNAs [50]. Work done in [60] shows that, by setting partial derivatives with respect to ‘p’ to zero, a rule for compensation of the circuit can be derived. Since we have written Gm as a function of electrical parameters of the LNA topology which also suffer from process variations, we can use the above method in (3.4) (3.4) 33 Variables with subscript ‘0’ represent values at the nominal process corner. Around the input match condition where RS = ωTLS, we write the total variation in Gm as: ΔΔ (3.5) (3.5) indicates that, in order to have no variation in the transconductance of the LNA, we must ensure that the variation on the input transistor’s transconductance must be zero. A detailed derivation of (3.5) is shown in Appendix A. Variations in the CSA Figure 3.2: Circuit diagram of the common source amplifier The common source amplifier (CSA) is a basic amplifying cell used in a variety of mixed signal applications. Shown in Figure 3.2, its gain is a strong function of the gm of the input transistor, 34 M1. By taking the partial derivatives with respect to process, similar to as done above, we can derive the following relationship for the overall transconductance: ΔΔ (3.6) In (3.6), we can see that, by eliminating variations due to process in gm, we can ensure that the variation in gain of CSAs can also be minimized. From (3.5) and (3.6), we realize that we need to eliminate variations in gm of the input transistor to eliminate gain variations. The LNA and CSA are examples of amplifiers where transconductance determines gain, therefore we need to develop a general method to eliminate variations in the input transistor’s gm to compensate for gain variations of similar amplifiers. Correction Scheme Proposed Solution In order to eliminate variations in transconductance due to process, we replace the Minput in Figure 3.1 and 3.2 with two input transistors in parallel. Figure 3.3 shows the modification made to the LNA as an example. The same change can be made to the input transistor of the CSA. The total input gm is now the sum of the individual gm of the transistors and our goal is for Δgmtotal = 0 in (3.7) for voltage gain variations of the amplifier to equal zero. 35 Figure 3.3: Circuit diagram of the compensated LNA. Transistors M1 and M2 are in parallel and form the input transistor of the LNA. A similar modification is made to the input transistor of the CSA To accomplish this, we want Δgm1 and Δgm2 to move in opposite directions with process variations. From Figure 3.3, (3.7) In the scheme, Vgs1 – the gate bias of M1 – is a set DC bias that does not vary. It can be generated from a bandgap reference or supplied externally. The nominal value of the DC bias Vgs2 of M2 is equal to Vgs1. We size M1 and M2 equally – both transistors are half the size of the input transistor in Figure 3.1 – and place them close to each other in layout to ensure that Vth1≈Vth2 [61]. For sub-micron transistors, , where and α represents the non-idealities due to short-channel effects [62]. With these conditions for the system: 36 () (3.8) Since Vgs2, Vth, and κ are process dependent terms, the variations in gm1 and gm2 with respect to disturbances in process are: ()[ () ( )] ()[ () ( (3.9) )] VOD,0 is the nominal gate overdrive voltage of M1 and M2 and κo is the nominal current gain. We express the total variation in gm of the transistors as: () (3.10) For Δgmtotal = 0, the condition on ΔVgs2 now becomes ΔΔΔ (3.11) We can extend the analysis previously shown in [63], to include the dependence of Δκ(p), i.e. the transistor’s current gain. Due to process variations, a positive Δκ, due to an increase in mobility and oxide capacitance, has the same impact as decrease in threshold voltage, which is increasing the transistor’s drive current. Therefore, it is equivalent to say that the second term of (3.11) can 37 be replaced with some fraction of -ΔVth. Based on this, we can represent the required bias for Vgs2 as: (3.12) Performing Monte Carlo simulations on the modified design in spectreRF for various values of Γ provides us with an optimum value of 2.8 which gives us the lowest variation in voltage gain of amplifiers for the TSMC 65nm CMOS process. The dependence of (3.11) on α allows the method to be applied to more advanced technologies as well. Before we present a circuit implementing (3.12), a discussion of the robustness of the scheme against changes in supply voltage and temperature is important to ensure reliable operation in various environments. Temperature Variation Recent studies have shown the adverse effects temperature variation has on power consumption, leakage, voltage gain, and noise performance of amplifiers [64][65]. In (3.8), the parameters that are most affected by temperature are the carrier mobility and threshold voltage of the transistor. From [66]: () (3.13) 38 where T0 and T are the reference and operating temperatures respectively. σµ is the mobility exponent constant between 1 and 2, and σv is the threshold voltage temperature constant ranging from 0.5 mV/K to 3 mV/K. We can derive the temperature dependence of transconductance of the uncompensated amplifier – gm,uncomp – from (3.13) as Δ Δ ( ( )) (3.14) For a temperature range of 273K to 323K and moderate inversion of input transistors, . The temperature dependence of the transconductance of the compensated amplifier is Δ Δ ( ( )) (3.15) Since the compensated circuit contains an extra , our scheme is able to minimize the temperature effect on gm due to the threshold voltage when compared to the uncompensated case. Supply Voltage Variation Increased transistor count due to transistor scaling and decreased supply voltages causes large IR and di/dt events. This leads to supply voltage variations on chip, adversely affecting the ICs performance [67]. Our scheme needs to be designed to minimize the impact of this variation on 39 the voltage gain of amplifiers as well. A detailed derivation of the supply voltage dependence on gain is provided in Appendix B. Here we summarize the results. For the uncompensated amplifier – biased with a constant dc bias – we obtain the variation in transconductance by taking the partial derivatives with respect to disturbances in VDD (represented by state variable ‘s’) as follows: (3.16) VOD,0 is the nominal overdrive voltage of the input transistor, RL is the output load impedance of the amplifier, and λ accounts for channel length modulation. From (3.16) we infer that gm,uncomp has a linear dependence of λ with respect to VDD. Hence the gain will also increase linearly with VDD. We have biased M2 of the compensated amplifier with a circuit representation of (3.12) which, as we will show in the next section, is designed to have a dependence on VDD as well. M1 is once again biased with a constant dc source. It must also be noted that at nominal VDD, M1 and M2 have approximately the same gate bias. To ensure that equals zero, we derive the following condition on the generated bias voltage. (3.17) Based on the nominal bias conditions of the amplifier and process parameters for the 65nm process, the slope in (3.17) equals -0.25. Therefore, by designing ΔVgs2 to have a dependence on 40 ΔVDD close to this value, we can eliminate all first order gain variations of the compensated amplifier with supply voltage. In the next section, we will discuss how we can engineer a bias circuit to exhibit this dependence with VDD while also generating (3.12). Compensation Circuit Design To generate a second compensating bias that will satisfy (3.12), we design a bias circuit shown in Figure 3.4 with the following properties: the output of the block must provide a DC bias which has a nominal value of Vgs1 and exhibit positive correlation with the threshold voltage with a slope of Γ. It must also have a dependence of approximately -0.25 to changes in supply voltage. All transistors in the four stage cascade configuration are biased in saturation and the output of the fourth stage provides us with (3.12). In Figure 3.4, β is a scaling factor generated from a resistive divider, and Aj2 is a width multiplier for transistors in stage j. Ratioing each stage gives us control over the bias circuit’s power consumption. 41 Figure 3.4: Circuit diagram of the bias circuit designed to compensate for process, temperature, and supply variations in the LNA First and Second Stage In order to analyze these stages, we apply KCL on the output nodes. At the output of the first stage, (3.18) By taking partial derivatives of Vo1 with respect to PVT variations, we get ΔΔ Δ (3.19) Similarly, and using the result from (3.19), the dependence of the output of stage 2 with respect to PVT is: 42 √ () (√ ( )) (3.20) Third Stage The output dependences of the third stage give us more control on the coefficients for ΔVth and ΔVDD. Following a similar analysis we get: √ (( )) (( √ )) (3.21) By choosing our constants κj and Aj, we can design the bias circuit to accurately compensate for variations in both threshold and supply voltage. Fourth Stage The fourth stage is used to primarily to adjust the nominal DC bias of the output. Following a KCL analysis on the output node, we can derive the dependencies of Vout in (3.22). √ (( √ ( ))) 43 (3.22) √ ( ( √ )) By adjusting the value of β and carefully sizing the fourth stage, we design Vout to have a nominal value of 0.5 V, which is chosen as an optimal value for the targeted voltage gain, noise, linearity, and power consumption for the 65nm technology. Since each term in (3.22) is a combination of well-defined constants over which we have complete design control, the design parameters shown in Table 3.1 are optimized for lowest gain variations due to process, temperature, and supply voltage. TABLE 3.1 DESIGN PARAMETERS OF THE BIAS CIRCUIT Design Parameter Value A1 A3 β √κ5/κ4 √κ2b/κ2a Γ ∆VDD coefficient 2.17 2.25 0.85 1.73 1.73 2.8 -0.18 Extracted simulation results in Figure 3.5 show the percentage variation of gm for transistors M1 and M2 in the compensated amplifier over a ±100 mV supply voltage sweep. We observe that gm of M1 and M2 move in opposite directions to cancel total Δgm over VDD. 44 Figure 3.5: gm of input transistors M1 and M2 in the compensated amplifier Performance of the Bias Circuit We simulate only the inductive degenerated LNA both with and without the bias circuit to see how accurately our method is able to compensate for process variations at every manufacturing corner. We also note the bias voltage generated at every corner and compare it to the optimum dc bias voltage required for Vgs2 to keep the voltage gain constant across all corners. Results are in Table 3.2. The CSA shows similar performance improvements. TABLE 3.2 PERFORMANCE OF THE BIAS CIRCUITS UNDER PROCESS CORNERS Corner % Variation of S21 of uncompensated LNA % Variation of S21 of compensated LNA Vgs2 generated by bias circuit (V) Required Vgs2 for zero S21 variation (V) TT 0 0 0.48 0.48 SS 29.83 4.5 0.64 0.70 FF 19.3 0.05 0.30 0.29 SF 19.02 2.45 0.58 0.60 FS 12.2 0.57 0.37 0.38 45 The bias circuit exhibits a maximum deviation of 60mV from the optimal value. The maximum gain variation from the TT corner is 4.50% as opposed to the base case of 29.83%, validating the scheme. The difference in sizes of the transistors and their relative distance causes some mismatch, which can affect the ability of the circuit to accurately track changes in threshold voltage. There is also some error from the mismatch of the two input transistors of the amplifier and variation of the resistive load. We have minimized these effects with common centroid layout techniques to eliminate gradient effects and dummy elements to mitigate LOD effects. Relative sizing of each stage allows us to keep the transistors small and limit the power consumption. In the next two sections, we take the reader through two design examples – a 3.2 GHz Low Noise Amplifier, and a Common Source Amplifier – to demonstrate the reduction in PVT variations with our compensation scheme. We present measured results for both topologies designed in the TSMC 65nm standard CMOS process fabricated over multiple wafer runs. Design Example I – 3.2 GHz Low Noise Amplifier Measured PVT Results of the LNA Figure 3.6 (a) and (b) show the histograms for the measured voltage gain of the uncompensated and compensated LNA, from 100 chips over multiple wafer runs. 46 Figure 3.6(a): Histogram of voltage gain of the uncompensated LNA over two wafer runs Figure 3.6 (b): Histogram of voltage gain of the compensated LNA over two wafer runs The uncompensated LNA has a voltage gain variation of 8.07% over two water runs while the compensated LNA has a much smaller spread and narrower shift in mean voltage gain over two runs with a standard deviation over mean gain of 2.19%. This is a reduction in variation of 3.7x. We also sweep the supply voltage for both the uncompensated and compensated LNA by ±10% to observe the effects of supply variation. Measurement results are shown in Figure 3.7. We measure the variation of the voltage gain of the uncompensated LNA due to supply voltage variations as 275 ppt/V. The variation in gain due to supply voltage variations is defined as where Gain(VDD,0) is the voltage gain at the nominal supply voltage and ΔGain(VDD) is the spread between Gain(VDD) and the nominal gain. In the compensated LNA, the voltage gain is almost constant over the entire supply voltage range. The variation is 29 ppt/V. It is noteworthy that we achieved an almost flat voltage gain over the supply voltage range without any post-fabrication calibration and process trimming. To measure the voltage gain across temperature, we use a probe station equipped with a vacuum 47 chamber. Liquid hydrogen cooling allows us to measure a temperature range of 273K to 373K. The temperature variation of the voltage gain is defined as where Gain(T0) is the voltage gain of the amplifier at room temperature (300K), and ΔGain(T) is the difference between Gain(T) – the gain at temperature T – and Gain(To). The measurement results are shown in Figure 3.8. With no bias compensation, the gain of the LNA varies as much as 2310 ppm/oC. By applying compensation, we lower the voltage gain variation of the LNA to 1554 ppm/oC. Figure 3.7: Gain of uncompensated and compensated LNA with supply voltage variations Figure 3.8: Gain of uncompensated and compensated LNA with temperature variation 48 The bias circuit occupies 0.0013mm2 and consumes 0.68 mW. The uncompensated LNA consumes 6.88 mW. The die photo of the compensated LNA is shown in Figure 3.9. Figure 3.9: Die photo of compensated LNA Impact on Input Matching, NF, and Linearity of the LNA Apart from voltage gain, process variation affects the input matching characteristics, noise figure, and linearity of LNAs and overall performance of wireless receiver systems, as indicated in (1). From [59], at the resonant frequency of the LNA, we design the real part of the input impedance – – to be as close as possible to the 50Ω impedance of the antenna or input source in order to maximize the return loss, i.e. minimize S11 of the LNA. Process variations will affect S11, causing the LNA to have a lower effective power delivery to the receiver chain. Since our scheme minimizes variation in gm, we expect variability in S11 to be minimized. Indeed, Testing 20 chips at random exhibit S11 of less than -11.0 dB at 3.2GHz when the compensation is applied as opposed to a worst case S11 of -8.0 dB for the uncompensated LNA. The Noise Factor of an inductive degenerated LNA is given in [70] as 49 () (3.23) where γ is the coefficient for channel thermal noise, ξ is the ratio of the device transconductance to the zero-bias drain conductance, Rg is the gate resistance of the input transistor, and gm,input is the nominal transconductance of the input device. In (3.23) we see a clear dependence of NF on gm,input and, expect some reduction with compensation. Measured data for 9 chips, in Figure 3.10 (a) and (b), show the expected reduction in NF. The average NF remains below 2.9 dB around the 3.2 GHz operating frequency of the LNA. This is comparable to previously reported LNAs operating in a comparable frequency range [68][69]. Figure 3.10(a): Measured NF of the LNA without compensation Figure 3.10(b): Measured NF of the LNA with compensation Third order intermodulation distortion can be expressed as [70]: (3.24) 50 gm,input is the input transconductance, gm3 is its second derivative, and RS is the input resistance. Monte Carlo simulations of the IIP3 in spectreRF show a σ/μ spread of 7.8% for the compensated LNA as opposed to 12.1% for the uncompensated LNA. Yield Analysis and Comparison to Other Work The compensation scheme increases the number of working LNAs by 25 if we introduce a lower bound gain constraint of 10 dB, the gain we design for in our prototype. We can determine a constraint for the upper bound on the gain, based on the input compression point of the next stage in the receiver, which is related to the power budget, and range of the wireless system. As an example, if the application is able to support a ±5% tolerance in the gain of the LNA, our compensation scheme increases the yield of working LNAs by 50%. Comparison with other published works is shown in Table 3.3. Our proposed scheme experimentally demonstrates the lowest gain sensitivity to variations in process. We also experimentally demonstrate supply voltage and temperature compensation of the LNA’s gain. We show comparable reductions in gain variation to the technique in [45] but consume less power and area since that scheme relies on off-chip hardware for external calibration of the LNA. [57] and [55] both use variation adaptive circuitry to compensate for gain variations in simulations but we demonstrate better PVT control with measured results. Our method shows higher measured yield improvements with less power consumption compared to the simulated results presented in [54] and [52]. Baseline LNA This Tech. 65nm CMOS 65nm Center Freq. (GHz) 3.2 3.2 TABLE 3.3 COMPARISON WITH OTHER WORK Target Gain (V/V) Process Varn. Varn. Redn. Yield inc. No. of chips measured 3 8.07 % - 100 3 2.19 % 72% 50% 100 Power 6.88 mW 7.69 mW Area 0.4 mm2 0.4 mm2 51 work [45] [55] [54] [52] [57] CMOS 0.25µm CMOS 0.13µm CMOS 0.25 µm CMOS 0.18 µm CMOS 0.18µm CMOS 1.9 2 1.8 3.1 – 10 2.4 3.67 3.62 % 28% 11.2 3.33 % 85% 5.62 N/R - 3.54 N/R - 1.73 13.48 % 47% 5.33 mW, 1.7 mm2, N/R 75 excluding excluding calib. calib. N/R Simulated N/R N/R 18% Simulated N/R N/R 27% Simulated 15 mW N/R N/R Simulated 410 µW 1.1 mm2 Design Example II – Common Source Amplifier We choose the Common Source Amplifier as another design example since it is one of the most efficient single transistor amplifiers that can be implemented in standard CMOS technologies. Measured results of over 88 samples of the CSA – shown in Figure 3.11(a) and (b) – indicate a reduction in variation of 3.8x. The performances of the uncompensated and compensated CSA in the presence of supply voltage variations are measured, similar to that of the LNA. The compensated CSA has a gain variation of 159 ppt/V with respect to varying supply voltage while the uncompensated CSA exhibits gain variation of 476 ppt/V. 52 Figure 3.11(a): Histogram of voltage gain of the uncompensated CSA over two wafer runs Figure 3.11(b): Histogram of voltage gain of the compensated LNA over two wafer runs Across temperature, with no bias compensation, the gain of the CSA varies up to 2885 ppm/oC. Applying compensation lowers the voltage gain variation of the CSA to 1669 ppm/oC. The results obtained have been summarized in Table 3.4 along with those from the LNA. Chip Type Uncompensated LNA Compensated LNA Uncompensated CSA Compensated CSA Wafer Run 1st 2nd 1st 2nd 1st 2nd 1st 2nd TABLE 3.4 SUMMARY OF MEASUREMENT RESULTS No. of Chips Meas’d Gain µ (V/V Gain σ Norm. Imp. over Std. baseline ) 50 3.29 0.179 5.44% 50 2.99 0.183 6.12% - 50 50 3.10 0.069 2.22% 3.05 0.057 1.96% 3.7x 44 2.85 0.167 5.85% 44 2.59 0.176 6.79% - 44 44 2.64 0.049 1.85% 2.67 0.048 1.79% 3.8x Temp. Varn. (ppm/o C) 2310 1554 2885 1669 Supply Varn. (ppt/V) 275 29 476 159 53 Conclusion In this paper, we develop a general design methodology to compensate for voltage gain variations of common amplifier topologies where gain is a strong function of transconductance. Our work is the first experimental demonstration of PVT compensation of the gain of amplifiers designed in a sub-micron process. Using statistical feedback to track changes in Vth due to process and temperature, and by generating an appropriate bias signal to the amplifier, we experimentally demonstrate – without any post-fabrication trimming or calibration – 3.7x reductions in gain variation of low noise amplifiers and common source amplifiers designed in the TSMC 65nm CMOS process. We also show that our scheme can successfully reduce variations arising from fluctuations in supply voltage. Results obtained from our design examples confirm that our scheme can easily be adapted to other amplifier topologies where transconductance determines gain such as differential amplifiers, common gate amplifiers, and operational transconductance amplifiers. Our compensation method occupies a small footprint and has a low power overhead of 9%, making it attractive for a variety of robust, low power, mixed signal systems. By regulating the gain of amplifiers, our scheme increases overall yield of systems, reduces costs, and decreases turnaround time. Appendix A Derivation of transconductance variation in the Low Noise Amplifier In this Appendix we present detailed calculation of the variation in Gm of the LNA with respect to process. The first order partial derivatives in (3.4) can be summed and simplified relative to the nominal Gm of the LNA as follows: 54 ΔΔ Δ ΔΔ (A1) Around the input match condition, RS = ωTLS, therefore (A1) can be simplified to: Δ ΔΔΔΔ ΔΔ (A2) Appendix B Derivation of gm variation with supply voltage We present a detailed derivation of (3.16) and (3.17) to account for how disturbances in VDD affect the voltage gain of the LNA and CSA. To simplify the analysis for the LNA, we can ignore the cascode transistor in the LNA since its primary function is input isolation and it doesn’t affect the current in the LNA. Variables with subscript ‘0’ represent nominal values. The total current – as a function of supply voltage ‘s’ – flowing through the amplifier is: () (B1) Vin,0 is the nominal dc bias of the input transistor and Vout is the dc voltage at the output node of the amplifier expressed as: 55 (B2) RL is the output impedance. The variation of Itotal due to disturbances in supply voltage is given as () (B3) Notice that Vin,0 has no dependence on VDD since the uncompensated amplifier is biased by a constant dc source. Combining (B2) and (B3), we can get: ( ( ) ) (B4) Taking the partial derivative of (B4) with respect to Vin,0 we get the following result for variation in gm,total: (B5) Vin,0 – Vth has been replaced by the nominal overdrive voltage VOD,0 of the input transistor. From (B5) we infer that gm,total, and hence the gain, has a linear dependence of λ with respect to VDD. In the case of the compensated amplifier, the dc input to transistor M2 – Vin2(s) – is generated by the bias circuit and therefore depends on VDD. M1’s bias – Vin1,0 – does not change with disturbances in VDD. The dc voltage at the output node is given as: 56 (B6) where I1 and I2 are currents flowing through transistors M1 and M2 respectively and are expressed as: () (B7) Taking the partial derivatives of (B7) with VDD, we get: () ( )( ) (B8) Combining (B6) and (B8) we can derive a dependence on Vout with respect to Vin2 as: ⁄ (B9) 57 At nominal VDD, . We can now calculate the variations in gm as follows by taking partial derivatives of the terms of (B8) with Vin1,0 and Vin2,0 respectively: (B10) [] In order for the gain to be independent of variations in VDD, we require From (B9) and (B10), the condition on becomes: to equal zero. (B11) 58 CHAPTER 4 Introduction PROCESS COMPENSATION OF OSCILLATORS Voltage controlled oscillators (VCO) are widely used in high speed clock recovery systems and as a precise clock for digital systems. Although crystal oscillators are excellent references and are stable with variations in supply voltage, temperature, and process, integrating them with onchip systems is difficult and expensive. Technology scaling beyond 90nm has made integrated circuits more vulnerable to die-to-die and within-die parameter fluctuations in the manufacturing process [71]. The challenge therefore lies in designing on-chip frequency references in CMOS that can tolerate worst case variations in process, temperature, and power supply. A lot of recent circuit design effort has been made to address this issue. Tschanz, et. al. [72] employ bidirectional adaptive body bias to maximize the number of dies that meet both the frequency and leakage constraints. This scheme, however, uses a reference crystal and post fabrication trimming to achieve its purpose, making it an expensive option. Sundaresan, et. al. [73], were able to achieve less than 3% variation in the frequency of a VCO by sensing the process corner in which the chip operates, but the scheme operates in the MHz range due to the assumption of its analytical model. Chen, et. al. ,[74] use a phase locked loop to counter variation but the external reference used makes it impractical for on-chip solutions. 59 System Design Concept To design a compensation loop for a low variation VCO, inspiration is derived from the PLL’s architecture where frequency differences between the VCO and a reference signal are translated to a voltage building up on a capacitor. Figure 4.1: System Diagram of the General Compensation Loop Based on the idea of a control loop feedback system, we propose the compensation system illustrated in Figure 4. 1. The signal from the VCO is fed to a digital unit which generates control signals for the frequency correction block. The correction unit generates a voltage VFS proportional to the period of the VCO. This voltage is then compared to VREF, a stable dc reference voltage. If VFS is higher than VREF, their difference will be positive and the VCO will be sped up. On the other hand, if VFS is lower than VREF, their difference will be negative and the VCO will be slowed down. The VCO’s frequency is corrected for process variations when VFS matches VREF. In this case, VCTRL reaches a stable value and the VCO settles to a particular 60 frequency. Using circuit components in the frequency correction unit which are robust to variations in process will give us a VCO with zero frequency variation. Unfortunately, circuit blocks on chip suffer from inherent variation due to effects discussed earlier. Nevertheless, novel designs of building blocks such as low variation current sources [76] assist in designing a stable, low variation, process compensated VCO without loading any critical high speed nodes. System Design The frequency sensing and correction block is implemented using a switched-capacitor technique, shown in Figure 4.2. Figure 4.2: Switched Capacitor based VCO tuning circuitry This section describes the implementation of various blocks used in the process compensation feedback system of the VCO. 61 Frequency Correction Unit The frequency correction unit is the most important component of the system since the stable, low variation, oscillation frequency of the system depends on proper functionality of this block. The architecture is based on a discrete time switched capacitor integrator and is shown in Figure 4.3. It consists of a current source Iref, capacitors C1 and C2, a high gain operational amplifier, transmission gate switches, and external inputs VREF and RST. Figure 4.3: Discrete time switched capacitor integrator An external RST is applied at the beginning of operation to clear all digital counters and establish a DC operating point for the output of the operational amplifier. Once the RST signal is deasserted, the VCO oscillates with its free running frequency. The output of the VCO is passed through a series of dividers to shape it into a square wave with a 50-50 duty cycle. The timing signal generator produces signals φAB, φA, φB, and φC based on digital logic. 62 AB  CLKx16 A  CLKx4  CLKx8  CLKx16 B  CLKx4  CLKx8  CLKx16 C  CLKx4  CLKx8  CLKx16 (4.1) Figure 4.4: Timing waveform controlling switches in the frequency sensor where CLKx4 is the waveform generated by dividing the output of the VCO by 4, as shown in Figure 4.4. Conventional CMOS logic was used in generating the control signals. Based on when the signals are asserted, the operation of the frequency correction unit can be divided into three stages: Initialization stage, Comparison stage, and Correction stage. Initialization Stage When φAB and φA are asserted, one plate of capacitor C1 is charged to VREF and the other plate is held at ground. This state is used to set an initial condition on C1 and allows for a comparison to be made between VREF and the voltage proportional to the system’s oscillation period. The charge contained in C1 at the end of the initialization stage is VREFC1. 63 Figure 4.5: Initialization Stage Comparison Stage When φAB and φB are asserted, one plate of the capacitor C1 is charged up by current source IREF for a period NTOSC, N being the divider ratio. The charge contained in C1 at the end of the comparison stage is VREFC1- NIREFTosc.The comparison stage establishes a charge difference at C1 which is proportional to the difference between the system’s current oscillation period and its nominal oscillation period. Figure 4.6: Comparison Stage 64 Correction Stage Once φAB is deasserted, capacitor C1 is floating and the charge on it is held. When φC is asserted, capacitor C1 is discharged by connecting one plate to ground and the other to the negative input of the operational amplifier. The high gain of the operational amplifier requires that its negative input also be a virtual ground as it tracks the positive input, which is set to ground. Since charge must be conserved, charge on the plate of C1 connected to the negative input of the operational amplifier is transferred to capacitor C2. Figure 4.7: Correction Stage The operational amplifier is designed as a conventional folded cascode to provide high gain so that both input nodes are able to track each other effectively. pFET transistors are used as input since the inputs to the operational amplifier are close to ground. The pFET input transistors are made large and square in layout to improve matching characteristics. Care is taken to ensure that the parasitic capacitance of the input transistors is much smaller than those used in the switched capacitor circuit. The op-amp is designed with a nominal gain of 35 dB. 65 Loop Stability The voltage at the output of the operational amplifier, VControl, increases proportional to the amount of charge transferred. This voltage does not change until the next occurrence of φc and sets the frequency of the VCO. After n cycles, the voltage at the output of the operational amplifier is updated according to the difference equation: Vctrl (n 1)  Vctrl (n)  I REF NTosc (n) C2 VREF C1 (4.2) where Vctrl(n) is the control voltage of the VCO and Tosc(n) is the oscillation period of the VCO in the nth step. The system will converge to a steady oscillation period when VREFC1=NIREFTosc. At this point, further values of VControl will equal their corresponding values in the previous cycle, indicating that the VCO has converged to its desired nominal oscillation period. Both capacitors C1 and C2 are on the order of pF so that they are much larger than the parasitic capacitances of the operational amplifier and the switches. The above simplified analysis doesn’t take into account the finite gain and input offset voltage of the operational amplifier in the loop. In order to properly analyze the stability and convergence of the loop, we need to re-write (4.2) introducing parameters A and Voffset representing the gain and input offset of the amplifier respectively. The relation between Vcontrol and the voltage at the negative input of the amplifier (Vx) can now be expressed as Vcontrol   A(Vx  Voffset ) 66 (4.3) Maintaining conservation of charge on capacitors C1 and C2 before and after switch S3 is closed, we get the following expression for Vx as Vx (n  1)  Vx (n) C2 (A 1) C1  C2 (A  1)  VREF C1 C1  I REF NTosc  C2 (A 1) (n) (4.4) and for Vcontrol as Vcontrol(n  1)  Vco n tro l( n ) C2 ( A 1) C1  C2 ( A  1)  Voffset C1  AC1 C2 ( A 1)   A I REF NTosc(n) VREF C1 C1  C2 ( A  1) (4.5) where Vcontrol(n) is the control voltage applied to the VCO in the previous correction cycle and Vcontrol(n+1) is the control signal that will be applied at the end of the current correction cycle. From (4.5), it is evident that, even in the presence of a finite gain, the compensation loop is stable and will still converge based on a first-order negative feedback exhibited by the third term, regardless of the starting condition. The static error Voffset will cause some amount of ripple on Vcontrol when VREFC1 = IREFNTosc but this can be minimized by increasing the ratio of C1 and C2 and ensuring the input transistors in the amplifier are well matched and large. Care must be taken not to make C2 too large as this would make the incremental voltage buildup on Vcontrol smaller, and hence, the compensation time larger. Making C2 small would lead to a loss of precision on 67 Vctrl, forcing it to periodically overshoot and undershoot the correct value. In our design a C1:C2 ratio of 1:3 was chosen. Accuracy Analysis In this section, we will analyze the factors that may limit the accuracy with which the switched capacitor configuration compensates the VCO for process variation. When the loop converges, Vcontrol (n+1)= Vcontrol (n) = Vcontrol ∞ and the oscillation period Tosc is represented as Tosc∞, where Tosc∞ = K’VCO. Vcontrol ∞. We can now determine how close Tosc∞ is to the ideal value of Tosc=VREFC1/NIREF by solving (4.6): Tosc  (VREF  Voffset )C1 N  I REF  C1 A.KV' CO  (4.6) The above expression shows that there is still some accuracy error present due to non-idealities in the compensation loop, similar to the error in the comparator based compensation loop. For most operational amplifiers, input offset error is in the range of less than ten millivolts [23] and can be further minimized by a number of proposed techniques [24]. This reduces the error in the numerator of (4.6) to less than 1.5% for VREF = 0.7. For an IREF = 300 µA, C1 = 1 pF, and K’VCO = 1.3 ns/V, the error in the denominator of (4.6) is less than 5%. Given the fact that Voffset< 8 bit current steering DAC Counter and SAR Logic Current Comparator IinA IinB>IinA Mismatch Detected IinA>IinB IinB Figure 5.31: Median Generation using a successive approximation approach In each cycle of approximation, the current of the replica median cell, IM, is compared with each of the 288 unit cells in the DAC matrix using a high-resolution 1-bit ADC current comparator. Its operation is discussed in the next section. Once all comparisons have been made, the binary DAC is updated based on whether IM lies in the upper or lower half of the current distribution. After 5 cycles of approximation – over 1000 Monte Carlo runs – this approach generates IM which tracks Iµ with an accuracy of 93.3%. High Resolution Current Comparator In order to compare IM with each of the unit cells in the DAC matrix, we have designed a high resolution current comparator with nonlinear sensing, as shown in Figure 5.32. This topology combines the advantages of high resolution and fast amplification for low current levels and reduced voltage swings at VA for larger current levels. 112 Figure 5.32: High Precision Current Comparator Figure 5.33: Sampling (fast) and averaging (slow) clocks used in comparison For well-matched MA and MB, I1 equals I2. When two current IinA and IinB are compared, IDiff then equals IinB – IinA. For positive IDiff, VA increases and VB decreases, causing MP to turn ON, creating a feedback loop. Similarly, for negative IDiff, MN turns ON. These voltage excursions are sampled by the two D flip flops to determine whether IinA > IinB or vice versa. Unfortunately, any mismatches between MA and MB will contribute to IDiff, causing incorrect mismatch detection. In order to minimize this, we use Dynamic Element Matching where we switch IinA and IinB feeding into MA and MB with a fast clock while sampling IDiff with a slow clock. This allows both IinA and IinB to equally sample the offset between MA and MB, averaging out their mismatch over the course of comparison. By doing this, we are able to detect as little as 5% mismatch between IinA and IinB, measured over 1000 Monte Carlo runs. 113 Eliminating Outliers Once IM has been generated, we can use the positional chart in Figure 5.22 to find IA, IB, IC, and ID for each row. Ranking unit cells in each row is accomplished with a time-to-digital converter using a current starved ring oscillator, which triggers an up-counter for a specified duration. The circuit topology is shown in Figure 5.34. Figure 5.34: Time-to-Digital converter The circuit has a resolution of 93nA and uses a 7-bit counter to digitize the current contribution from every unit cells. These values are stored in registers and compared to a digital representation of IM to determine outliers. Cost of Calibration on Overall DAC Design The additional calibration circuitry utilizes minimum sized logic and switches and increases the required area by an additional 11% on top of the DAC matrix. With two bits of redundancy per row and the designed calibration blocks, we still achieve a reduced DNL with 40% less area usage as compared to simply increasing the current driving PMOS transistor, confirming that the benefits of calibration outweigh cost in complexity and area. 114 Figure 5.35: DNL reduction taking area occupied by the calibration circuitry into account Conclusion In this chapter we propose two techniques to lower non-linearity errors in thermometer current steering digital-to-analog converters, which occur due to increasing mismatch among unit current cells in advanced CMOS processes. The first technique we discuss introduces additional current sources in the DAC and eliminates outliers to reduce the error distribution among units. The redundancy in unit sources is a small price to pay in terms of area and power but with increased reduction in mismatch and hence DNL and INL errors in the DAC. Measured results of an 8-bit DAC designed in the TSMC 65nm CMOS technology confirm that redundancy leads to 38% reduction in DNL and 28% reduction in INL. The second technique reorders rows of the 2-dimensional DAC to minimize accumulation of errors and therefore reduce INL error of the DAC. Measured results show a further 30% reduction in INL error of the DAC. The two techniques combined show a 48% reduction in INL error. 115 We also discuss circuit solutions to implement both redundancy and reordering on-chip and demonstrate that the calibration circuitry improves both DNL and INL errors with 40% less area usage than by simply making unit current cells larger to limit their mismatch. This confirms that implementation of both redundancy within elements and reordering of rows of a thermometer DAC offers superior performance with a cheaper power overhead and area footprint, making it a viable solution to decrease errors in thermometer DACs required for precise calibration in a wide variety of wireless and wireline applications. 116 CHAPTER 6 Conclusion CONCLUSION AND FUTURE WORK The goal of this dissertation is to present on-chip circuit compensation techniques to reduce the adverse effects of process variation in advanced CMOS mixed signal circuit blocks. Circuit performance is increasingly impacted by process variation and it becomes more expensive to perform post-fabrication techniques to bring performance of ICs closer to their nominally designed specification. In this dissertation, we have presented two techniques to overcome the adverse effects of process variation in low-noise amplifiers and voltage controlled oscillators. We designed a novel bias circuit using statistical feedback to measure changes in threshold voltage, which occur due to variations in process, supply voltage, and temperature. The error signal generated is fed back to one of the inputs of the LNA to compensate for variations in overall transconductance of its input transistor, and hence the voltage gain. By compensating for variations in transconductance, we are also able to reduce variations in noise figure and input match of the LNA. Measured results of 100 LNAs over two wafer runs in the TSMC 65nm CMOS process show a 3.6x reduction in voltage gain variations due to process variation. Our scheme also decreases gain variations due to temperature changes from 2310 ppm/oC to 1554 ppm/oC and due to supply voltage changes from 275 ppt/V to 29 ppt/V. Our technique is scalable with process and can be applied to other types of amplifiers where transconductance determines gain and we demonstrate similar reductions in gain variation for a common source amplifier. 117 We also designed a switched-capacitor based feedback scheme that tracks drifts of center frequency of a current starved ring oscillator (CSRO) that occur due to variations in process and temperature. The designed circuit generates an error signal to compensate for this change. Measured results for CSROs designed in the IBM 90nm CMOS process reduce the spread in center frequency from 15.2% to 6.2% and decrease the spread to less than 1% across temperature. As processes scale, random mismatches among identically designed circuit blocks becomes increasingly exacerbated. This affects the performance of various circuit blocks where accurate matching of circuit units is extremely important, such as resistors in a resistor ladder and DAC, differential input pairs in a comparator bank, and sensing transistors in imagers. In this dissertation, we study how mismatch of unit current cells in a thermometer current steering DAC affects its non-linearity performance. Instead of making the cells larger to reduce mismatch at the expense of increased area and power, we propose two new techniques – redundancy among current units, and reordering of unit cells – to improve both DNL and INL performance of such DACs. Redundancy among unit cells is used to remove outlier elements from the DAC to reduce the overall error and mismatch of unit cells. Using two redundant elements per row of a two dimensional DAC reduces DNL and INL error by 38% and 28% respectively in an 8-bit thermometer current steering DAC designed in the TSMC 65nm CMOS process. Reordering of unit elements reduces overall error accumulation in the DAC. In our two-dimensional DAC design, we alternate between rows with opposite error signs. Measured results show an additional 30% error reduction in INL. 118 Future Work The techniques we have presented in this dissertation reduce the effects of variation on performance of various mixed signal blocks that can be used in a variety of wireline and wireless systems. A natural succession to the work presented is to focus on studying the effects of variation on larger systems and combining some of the techniques we have proposed to improve yield across process, temperature, and supply voltage. Preliminary work has been demonstrated by Gangasani, et. al. in [107]. Systems can also be optimally designed to improve an overall metric such as yield, power, and speed, instead of just variation reduction of a specific electric parameter. Work shown in [108] by Dutta propose a sizing algorithm to improve overall profit of ICs rather than overall yield. On-chip compensation circuit techniques are a great tool for designing robust mixed signal circuits and systems without large overheads in area, power, and cost. By targeting the metric whose variation we are controlling and narrowing down the electrical parameters in CMOS devices which contribute to its variation, we can derive inspiration from a wide variety of feedback techniques and statistical solutions to design self-healing circuit topologies which track and adapt to changes in process, temperature, and supply voltage. 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