Engineering Surface Morphology at the Atomic Level with Applications in Electronic Materials

dc.contributor.authorValerian, Ignatescu
dc.description.abstractThe silicon (111) and (001) surfaces have wide technological importance. Control of the morphologies of these surfaces at the atomic level is vital for such applications as layer-by-layer growth or assembly of nano-scale devices. We have developed techniques to create large areas with no or widely spaced atomic steps on patterned silicon surfaces by high temperature annealing in ultra-high vacuum (UHV). At annealing temperatures high enough to promote surface premelting, large liquid-like structures form and are preserved during quenching on regions with low step-density since these areas have no efficient sinks to absorb diffusing atoms. Based on the surface morphologies observed by atomic force microscopy, we suggest a sequence of events for the evolution of the silicon surface, from the onset of surface premelting up to the bulk melting temperature. Large dendritic islands observed on the more slowly cooled down Si(111) samples are attributed to the persistence of surface melted structures and to non-equilibrium ?condensation? of the excess adatoms from the (1x1) ? (7x7) phase transition. The effect of UHV high temperature annealing on the Si(111) surface is an initial increase in the measured surface roughness due to Ostwald ripening followed by a surface smoothing to become atomically flat. The boundaries of etched craters or mesas initially develop profiles upon annealing that conform to the predictions of continuum theory of surface transport. As an application, we built MOS capacitors on three types of Si(111) surfaces viz. atomically flat surfaces, normal (stepped) surfaces cleaned in UHV by high-temperature annealing and normal, RCA cleaned wafer surfaces. The leakage current through the oxide was measured for all three cases. Our results show that the smoother the surface before oxidation, the smaller the leakage current. In another application Si(111) substrates with regular arrays of atomic steps were used to induce azimuthal alignment of crystals in thin pentacene films. Pentacene films deposited on heated samples, at a low deposition rate, show significant azimuthal alignment of the pentacene crystals relative to the atomic steps, with the (110) pentacene planes being parallel to the atomic steps.en_US
dc.description.sponsorshipCornell Center for Materials Research (CCMR) grant number DMR-0079992 National Science Foundation (NSF) grant number DMR-0109641en_US
dc.format.extent5474896 bytes
dc.identifier.otherbibid: 6476319
dc.subjectatomic stepsen_US
dc.subjectsurface pre-meltingen_US
dc.subjectstep-free surfacesen_US
dc.subjectsurface morphologyen_US
dc.subjectetched cratersen_US
dc.subjectUHV annealingen_US
dc.subjectdendritic islandsen_US
dc.subjectfractal dimensionen_US
dc.subject(1x1) to (7x7) phase transitionen_US
dc.subjectMOS capacitoren_US
dc.subjectFowler-Nordheim tunnelingen_US
dc.subjectleakage currenten_US
dc.subjectstepped substrateen_US
dc.subjectazimuthal alignmenten_US
dc.subjectthin filmen_US
dc.titleEngineering Surface Morphology at the Atomic Level with Applications in Electronic Materialsen_US
dc.typedissertation or thesisen_US
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