Profiling Infrastructure for the Performance Evaluation of Asynchronous Systems

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Designing and optimizing large-scale, asynchronous circuits is often an iterative process that cycles through synthesis, simulating, benchmarking, and program rewriting. Asynchronous circuits are usually specified by high-level, sequential or concurrent programs that prescribe the intended behavior. The self-timed nature of the interface gives designers much freedom to refine and rewrite equivalent specifications for improved circuit synthesis. However, at any step in the design cycle, one faces an uncountable number of choices for program rewriting ? one simply cannot afford to explore all possible transformations. Informed optimizations and design space pruning can require detailed knowledge of the run-time behavior of the program, which is what our simulation trace analysis infrastructure provides. Tracing entire simulations gives users the opportunity to understand program execution in great detail. Most importantly, trace profiling captures typical run-time behavior and input-dependent behavior that cannot always be inferred from static analysis. Profiling provides valuable feedback for optimizing both high-level transformations and low-level netlist synthesis.

To address this need for profiling, we present a framework for analyzing the simulated execution of high-level, concurrent programs, as a foundation for iterative optimization and synthesis of asynchronous circuits. The framework includes a Scheme environment and a library of primitive procedures for handling and querying trace data. Interactivity is essential for analysis sessions where the sequence of queries to execute is not known a priori. The initial library also includes procedures for some frequently run analyses (built on top of the primitives). Providing an interface for working directly with the simulation and trace data structures makes analysis development within our framework both flexible and convenient. The extensibility of our framework enables compilation-free development and prototyping of custom analysis routines, so users can easily share and build upon the work of others. The primary purpose of this analysis framework is to enable future tools to use profile-driven feedback in automating iterative optimization and design-space exploration.

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asynchronous circuits; profiling; trace; analysis


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