Self-Timed Length-Adaptive Arithmetic

dc.contributor.authorBingham, Edward Arthur
dc.contributor.chairManohar, Rajiten_US
dc.contributor.committeeMemberBatten, Christopheren_US
dc.contributor.committeeMemberZhang, Zhiruen_US
dc.date.accessioned2023-04-04T19:05:52Z
dc.date.available2023-08-24T06:00:18Z
dc.date.issued2020-12
dc.description253 pagesen_US
dc.description.abstractDiminishing returns in technology scaling has motivated a resurgence of exploration into new computer architectures. While Coarse Grained Reconfigurable Arrays show promise in accelerating commonly used complex operations, their overall capacity remains fairly limited. While there is pressure on general purpose systems to support wide operations, the typicalworkload mostly exercises the lower 10 to 15 bits. This leaves most of the array on and unused during normal operation. This thesis presents adaptive digit-serial arithmetic as a plug-and-play method to support a variety of bitwidth requirements, showing decreased energy and area alongside increased throughput.en_US
dc.description.embargo2025-09-15
dc.identifier.doihttp://doi.org/10.7298/d777-1750
dc.identifier.otherBingham_cornellgrad_0058F_12312
dc.identifier.otherhttp://dissertations.umi.com/cornellgrad:12312
dc.identifier.urihttps://hdl.handle.net/1813/113066
dc.language.isoen
dc.subjectAdaptiveen_US
dc.subjectArithmeticen_US
dc.subjectAsynchronousen_US
dc.subjectSerialen_US
dc.titleSelf-Timed Length-Adaptive Arithmeticen_US
dc.typedissertation or thesisen_US
dcterms.licensehttps://hdl.handle.net/1813/59810.2
thesis.degree.disciplineElectrical and Computer Engineering
thesis.degree.grantorCornell University
thesis.degree.levelDoctor of Philosophy
thesis.degree.namePh. D., Electrical and Computer Engineering
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