Diminishing returns in technology scaling has motivated a resurgence of exploration into new computer architectures. While Coarse Grained Reconfigurable Arrays show promise in accelerating commonly used complex operations, their overall capacity remains fairly limited. While there is pressure on general purpose systems to support wide operations, the typicalworkload mostly exercises the lower 10 to 15 bits. This leaves most of the array on and unused during normal operation. This thesis presents adaptive digit-serial arithmetic as a plug-and-play method to support a variety of bitwidth requirements, showing decreased energy and area alongside increased throughput.