Adaptive And Inexact Approaches For Energy-Efficient And Variation-Aware Nanometer Vlsi Design

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Adaptive circuit design technique and error-tolerant computing have both been suggested as potential methodologies for addressing two major hurdles facing the future of semiconductors: increasing variability and decreasing energy-efficiency, both of which becoming especially prominent as transistor scaling becomes increasingly aggressive with gate lengths down to sub-20nm and below. Adaptive circuit design partially relaxes the operating safety margins by dynamically adjusting system parameters such as supply voltage, body bias, and operating frequency; however, it cannot fully eliminate such margins since it must guarantee computational correctness in all cases including the worst-case combinations of extreme variations. Error-tolerant computing such as error detection/correction or resilient hardware has been proposed to relax these margins. While some of the potential benefits of error-tolerant computing have been revealed, their implementation requires a significant amount of design, power, and complexity overhead. This dissertation presents a novel methodology to relax some of the design tradeoffs present in current adaptive circuit design techniques by employing a double-gate MOSFET (DGMOSFET) device as the main circuit element, and introduces a more efficient error-tolerant computing framework, which will hereby be referred as "Inexact Computing" in this dissertation. This dissertation presents the implementation of adaptive circuit design techniques using an independently-biased back-gated DGMOSFET, the details of which includes the theory of the DGMOSFET device modeling, new design techniques for compensating parametric variations, and achieving better energy-efficiency and noise robustness. Threshold voltage tuning using back-gate of the DGMOSFET was compared with a conventional body-bias method. This technique is a promising solution to control the transistor's threshold voltage while reducing undesirable effects at the sub-50 nm device technology nodes. An automatic adaptive circuit for threshold voltage tuning was implemented using DGMOSFET devices in 45nm CMOS technology. Simulation results show that this circuit compensates for static and dynamic variations. This adaptation approach using DGMOSFETs along with adaptive supply voltage scaling allows simultaneous optimization of power and performance according to application-specific workload and requirements. Simulation results using a 45nm CMOS technology indicate that this adaptive circuit design can provide 50% higher performance for the same energy, or consume 40% less energy for the same performance. In contrast to conventional methods which only employ dynamic voltage scaling, adaptive tuning of threshold voltages reduces power consumption while maintaining high noise margin. As another solution for mitigating variability and power issues, this dissertation also introduces the theoretical framework for probabilistic circuit representations of conventional CMOS digital logic and reveals the relationship between the error probabilities vs. energy. Using probabilistic modeling in sub-50nm silicon transistor technology, the relationship between statistical uncertainties and errors are elucidated for different configurations and topologies and design the trade-offs are quantified. Gate-level implementation of the probabilistic CMOS logic is validated by circuit simulations of a commercial 45nm SOI CMOS process technology. Presenting as an example a practical ALU architecture where voltages can be scaled from most significant to least significant bit blocks, the potential benefits of this technique are shown. A calculation error of 10-6, an error rate quite tolerable for many computational tasks, is shown to be possible with a total power reduction of more than 40%. More importantly, the relation of error probabilities and energy from our probabilistic approach follows the second law of thermodynamics, regardless of scale or topology of a circuit. Finally, this dissertation verifies the suggested relationship of error vs. energy by a prototype image signal processing system implemented on an FPGA. The processing of a 2D RGB color image using this prototype is used to verify this relationship. For each R, G, and B color component, 2D 3-tap FIR image filters are implemented using hard IP of the FPGA. Measurements were performed using programmable pulse generators and a logic analyzer to minimize the dependency on FPGA synthesis and place/route design flows. Subsequent experiments demonstrate the feasibility of using inexact computing for specific error-tolerant applications such as human vision. An image processing error of 1.2x10-6 is shown to provide acceptable image quality while reducing the total power consumption by 30%.

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Union Local


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Tiwari, Sandip

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Manohar, Rajit
Kan, Edwin Chihchuan

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Electrical Engineering

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Ph. D., Electrical Engineering

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Doctor of Philosophy

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