Process Invariant Circuit Techniques For Reliable Mixed Signal Systems

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CMOS scaling has enabled circuit designers to develop a wide variety of fully integrated mixed signal systems by taking advantage of the high switching speeds and lower noise figures offered by these devices. Unfortunately, scaled CMOS increasingly suffer from large variations in expected performance due to defects in manufacturing and fluctuations in environmental conditions. This phenomenon is termed as process variation and it ultimately impacts yield of mixed signal systems. Post fabrication tuning efforts to correct for these effects is an expensive solution and, in some cases, infeasible. This work proposes a variety of circuit techniques to combat variations in standard mixed signal blocks such as low noise amplifiers (LNA), voltage controlled oscillators (VCO), and digital to analog converters (DAC). An on-chip statistical technique, designed in the TSMC 65nm CMOS process, tracks changes in threshold voltage due to variations in process, temperature, and supply voltage, and provides an error correction signal to the LNA. Silicon measurements show that our technique reduces the variation in voltage gain of LNAs by a factor of 3.6. We also demonstrate that this technique can be applied to other amplifiers designed in advanced CMOS processes and demonstrate with a common source amplifier. A switched capacitor based feedback loop, designed in the IBM 90nm CMOS process , generates an error signal based on the drift in the center frequency of VCOs and provides an appropriate correction signal to compensate for the drift. Measured results show a 2.5x reduction in center frequency variation of the VCO. We propose using redundancy in a DAC to tighten the error distribution of DAC elements and improve non-linearity. Measured results of an 8 bit thermometer current steering DAC designed in the TSMC 65nm CMOS process show 38% reduction in non-linearity. Another technique to reduce non-linearity is reordering of elements based on their error distribution. This reduces non-linearity by an additional 30%. Combining both schemes significantly reduces induced non-linearity errors with minimal area and power increase.

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Apsel, Alyssa B.

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Afshari, Ehsan
Zhang, Ke

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Electrical Engineering

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Ph. D., Electrical Engineering

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Doctor of Philosophy

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