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Logical Accelerators on Manycore Processors

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Abstract

Traditional general-purpose processors emphasize finding parallelism using hardware control logic, but this logic is energy inefficient and will limit future performance improvements. Manycore processors offer a contrasting approach for general-purpose computation: find parallelism in software and remove energy inefficient hardware control logic. Manycores offer up to thousands of programmable threads that can efficiently target applications with thread-level parallelism (TLP). However, manycores have not yet gained market adoption due to the difficulty of programming and lack of performance on applications containing data-level parallelism (DLP) and instruction-level parallelism (ILP). This thesis proposes to use software reconfiguration to improve manycore performance on various classes of applications with little hardware overhead. We propose two designs where software can group together existing hardware resources of adjacent cores to form logical accelerators. Rockcress adds lightweight hardware to enable the formation of a logical vector unit to accelerate applications with DLP. Watercress adds lightweight hardware to enable the formation of a logical CGRA to accelerate applications with ILP. These techniques will expand the set of applications that can enjoy the performance and computational density of manycore architectures.

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142 pages

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2023-08

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Union Local

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Committee Chair

Sampson, Adrian

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Committee Member

Batten, Christopher
Zhang, Zhiru

Degree Discipline

Electrical and Computer Engineering

Degree Name

Ph. D., Electrical and Computer Engineering

Degree Level

Doctor of Philosophy

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Government Document

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Attribution 4.0 International

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dissertation or thesis

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