Most bit serial computation is done least significant bit first (LSB) because it is a natural implementation of the carry chain. However, number comparisons need to start at the most significant bit (MSB) making MSB-first logic very important for executing programs with a lot of comparisons. This paper presents the design of an asynchronous bit serial MSB-first adder that uses a conventional two's complement binary encoding. The adder can process varying unmatched input bit lengths at run time and produce the minimal bit length addition result. However, since it has a data-dependent output latency, it is only suitable only for an asynchronous implementation. We compare this adder to an asynchronous bitserial LSB-first adder and a bit-parallel carry ripple adder in HSPICE using a 90nm process. The results will show that this MSB-first adder uses 3.15 times the energy as the analogous LSB-first adder. It also produces the most significant bit 1.10 times faster than the LSB-first adder and carry ripple adder. Optimizations made to a constant-response time counter used in the design are also described.