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Back Side Charge Trapping Nano-Scale Silicon Non-Volatile Memories

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dc.contributor.authorSilva, Helena G
dc.date.accessioned2005-07-22T12:16:00Z
dc.date.available2005-07-22T12:16:00Z
dc.date.issued2005-07-22T12:16:00Z
dc.descriptionSandip Tiwari Lester Eastman Joel Brocken_US
dc.description.abstractA new alternative device structure for scalable silicon non-volatile memories was investigated. The difficulties in scaling current devices arise from the non-scalability of the gate stack formed by the tunneling oxide, floating gate and control oxide. The proposed device is based on storage of charge in silicon nitride traps in the back of a thin single crystal silicon channel. This is intrinsically different from conventional silicon non-volatile memory structures, in which charge is stored between the silicon channel and the gate. The devices are fabricated on a modified silicon-on-insulator substrate that employs a stack of silicon oxide ? silicon nitride ? silicon oxide as the buried insulator. The charge trapping layer, silicon nitride, is separated from the silicon channel by a thin tunneling oxide and from a back gate by a thicker blocking oxide. The device is written and erased by applying an electric field between the back gate and source and drain that causes charge to tunnel between the silicon channel and the trapping layer. When there is no voltage applied, charge is retained in the silicon nitride, hence the non-volatility of the memory. Charges stored in the silicon nitride traps change the potential of the silicon channel resulting in a threshold voltage shift of the device that is sensed using the front gate. The decoupling of the read function (front) from the write and erase functions (back) gives this device a unique advantage in scalability and the ability to operate simultaneously as a high performance transistor and as a non-volatile memory. Back side charge trapping non-volatile memory devices were demonstrated for the first time. The fabrication process is described and the electrical characteristics are presented. Fabricated devices exhibit memory operation down to 50 nm gate length and double gate operation down to 20 nm gate length. The memory characteristics of the devices, programming times, cycling endurance and retention time are comparable to those of conventional front side storage devices. The new device has the potential to be scaled to 10 nm gate length, a significant improvement from current devices, for higher density and lower power semiconductor non-volatile memory.en_US
dc.description.sponsorshipNational Science Foundation through the Cornell Center for Materials Research, Foundation for Science and Technology (Portugal), European Social Fund (Third Community Support Framework)en_US
dc.format.extent1390360 bytes
dc.format.mimetypeapplication/pdf
dc.identifier.otherbibid: 6475810
dc.identifier.urihttps://hdl.handle.net/1813/2104
dc.language.isoen
dc.subjectsemiconductor non-volatile memoryen_US
dc.subjectflash memoryen_US
dc.subjectflash memory scalingen_US
dc.subjectback side storageen_US
dc.subjectback side charge trappingen_US
dc.subjectnano-scale memoryen_US
dc.subjecttrapsen_US
dc.subjectsilicon nitride trapsen_US
dc.subjectelectron beam lithographyen_US
dc.subjectRandom Telegraph Signalen_US
dc.subjectsilicon - silicon oxide - silicon nitride - silicon oxide - siliconen_US
dc.subjectSONOSen_US
dc.subjectONOen_US
dc.subjectback SONOSen_US
dc.subjectmobilityen_US
dc.titleBack Side Charge Trapping Nano-Scale Silicon Non-Volatile Memoriesen_US
dc.typedissertation or thesisen_US

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