New Single Element Memory Transistor With A Phase Transition Thin Film Material As A Gate Insulator

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A new single element phase transition memory with a gate insulator composed of a phase transition film and two silicon dioxide layers is proposed. A phase transition thin film is placed between silicon dioxide layers and hence the gate stack of the transistor has a metal -insulator -phase transition material -insulator -semiconductor (MIPIS) structure. I n my experiments, Vanadium Dioxide (VO2), Germanium Antimony T elluride (GST) and Samarium Nickelate ( SmNiO3) are employed as intermediate gate insulators, and bulk-type and suspended channel device structures are implemented. These materials go through structural phase transition with the increase of temperature and their physical properties, such as resistance, reflectance and permittivity, change drastically. The original proposition is that J oule heat induced by current flowing through the channel leads to the phase transition of a material and thus modulates the threshold voltage of a memory transistor. Polarization effect, however, dominates over the phase transition effect in fabricated devices. The counterclockwise voltage hysteresis of gate capacitance is observed in response to the gate voltage a nd consistent with the hysteretic behavior resulting from polarization switching. In VO2 bulk -type devices, memory window of ~1 V is obtained in -4 to 4 V gate voltage cycling. Its remnant polarization of ~0.53 [mu]C/cm2 a nd coercive field of ~450 kV/cm are extracted from the saturation behavior of threshold voltage shift. Similar to other ferroelectric memory stru ctures, the depolarization field exists. The state of memory devices decays gradually and retention times of approximately 15 minutes are obtained at room temperature. Assuming the second order ferroelectric phase transition, the Curie-Weiss temperature of VO2 is extrapolated and its value is around 450 K. At lower temperatures, the polarization of VO 2 disappears due to the freezing of switchable polarization. I n GST suspended channel devices, hysteresis memory window of ~1 V u nder ±4 V cycling and r etention times of hundreds of seconds are obtained. Extracted remnant polarization is ~0.13 [mu]C/cm2. The degradation of the polarization and charge trapping effect are observed at low temperature. I n SNO bulk -type devices, space charge polarization is domi nant given the fact that the response time of polarization is above 1 [mu]s. Hysteretic behaviors induced by the space charge polarization are explained by Poole-Frenkel charge trapping/detrapping mechanism. The stored information decays gradually with the retention time of the order of ten seconds at room temperature.

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Memory; Phase Transition; Ferroelectric; vo2; gst; sno; Polarization; Hysteresis; mosfet


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Tiwari, Sandip

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Kan, Edwin Chihchuan
Van Dover, Robert B.

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Electrical Engineering

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Ph. D., Electrical Engineering

Degree Level

Doctor of Philosophy

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Government Document




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dissertation or thesis

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