Silicon photonics has the potential to enable continued scaling of computing performance by providing efficient high speed interconnects within and between logic processors, memory, and other peripherals, which are currently limited by fundamental limits of RF attenuation and spatial bandwidth density of electrical interconnects. However, the path to high performance, cost effective, and scalable integration of silicon photonics with CMOS microelectronic components has not been clear. In this dissertation, we present the vision of the Backend Deposited Silicon Photonics (BDSP) platform that can seamlessly integrate silicon photonics with CMOS microelectronics without disrupting the CMOS fabrication process. Every aspect of BDSP platform, including excimer laser annealed polycrystalline silicon, low loss silicon nitride waveguide, modulator, detector, electrical interface, backend CMOS compatibility, and 3D waveguide integration, is discussed in detail. We experimentally demonstrate key components of the backend deposited silicon photonics platform. We experimentally establish the post processing thermal budget limit for a 90 nm bulk CMOS process as 400? C for 90min. We then demonstrate fabrication of high quality passive polysilicon optical resonators with quality factors above 12,000 using excimer laser anneal. Building on this work, we demonstrate gigahertz electro-optic polysilicon modulator compatible with CMOS backend integration and also show photodetector operation. Optical resonators and waveguides monolithically integrated on CMOS and 3D integration of silicon nitride waveguide and polysilicon waveguide are also demonstrated. In addition, we demonstrate quasi-linear electro-optic phase modulation in silicon using optical mode and PN junction engineering. Finally, results are summarized and possible future works based on BDSP are discussed. This demonstration of the proposed backend deposited silicon photonics opens up a whole new horizon to silicon photonics integration on CMOS. By decoupling CMOS fabrication from photonics fabrication, we lower the barrier to introducing silicon photonics into CMOS foundries and potentially accelerate the adoption of silicon photonics.