Cross-Stage Logic and Architectural Synthesis: with Applications to Specialized Circuits and Programmable Processors
| dc.contributor.author | Liu, Gai | |
| dc.contributor.chair | Zhang, Zhiru | |
| dc.contributor.committeeMember | Lal, Amit | |
| dc.contributor.committeeMember | Studer, Christoph | |
| dc.contributor.committeeMember | Sampson, Adrian L | |
| dc.date.accessioned | 2019-04-02T14:00:01Z | |
| dc.date.available | 2019-04-02T14:00:01Z | |
| dc.date.issued | 2018-12-30 | |
| dc.description.abstract | Technology scaling, architectural innovations, and electronic design automation (EDA) are the three pillars supporting the exponential growth in computer hardware performance for the past six decades. With the traditional CMOS scaling approaching its end, there is an urgent need to explore novel techniques in the latter two aspects to sustain the long-standing trend of ever increasing computing performance and energy efficiency. This thesis studies new logic and architectural synthesis techniques that aim to significantly improve both productivity and quality for the digital hardware design. We re-examine the boundaries in the traditional EDA flow with the goals of (i) identifying and overcoming deficiencies in existing, well-established logic-level optimization methods, and (ii) raising the level of abstraction to ease architectural-level exploration for hardware specialization. A common theme in this thesis is cross-stage optimization, where the synthesis decisions at an early stage are made aware of downstream optimization in an efficient manner to maximize the quality of results (QoRs). More specifically, we apply cross-stage optimization to tackle four challenging synthesis problems at logic and architectural level. At the logic level, we investigate both exact and approximate synthesis techniques: (P1) PIMap improves the quality of logic optimization by iteratively restructuring the logic network guided by technology mapping; (P2) SCALS generates approximate circuits with statistical guarantees. At the architectural level, we target both specialized and programmable engines: (P3) ElasticFlow compiles irregular loop nests into specialized accelerators optimized for average-case performance; (P4) ASSIST synthesizes an instruction set architecture (ISA) description into programmable processor. | |
| dc.identifier.doi | https://doi.org/10.7298/1hqw-wc85 | |
| dc.identifier.other | Liu_cornellgrad_0058F_11162 | |
| dc.identifier.other | http://dissertations.umi.com/cornellgrad:11162 | |
| dc.identifier.other | bibid: 10757995 | |
| dc.identifier.uri | https://hdl.handle.net/1813/64855 | |
| dc.language.iso | en_US | |
| dc.subject | Architectural Synthesis | |
| dc.subject | Cross-Stage Optimization | |
| dc.subject | Electronic Design Automation | |
| dc.subject | Logic Synthesis | |
| dc.subject | Computer engineering | |
| dc.subject | Engineering | |
| dc.title | Cross-Stage Logic and Architectural Synthesis: with Applications to Specialized Circuits and Programmable Processors | |
| dc.type | dissertation or thesis | |
| dcterms.license | https://hdl.handle.net/1813/59810 | |
| thesis.degree.discipline | Electrical and Computer Engineering | |
| thesis.degree.grantor | Cornell University | |
| thesis.degree.level | Doctor of Philosophy | |
| thesis.degree.name | Ph. D., Electrical and Computer Engineering |
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