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dc.contributor.authorLin, Hao
dc.date.accessioned2007-05-03T19:07:02Z
dc.date.available2007-05-03T19:07:02Z
dc.date.issued2007-05-03T19:07:02Z
dc.identifier.otherbibid: 6475892
dc.identifier.urihttps://hdl.handle.net/1813/7553
dc.description.abstractOriginating in an effort to advance electronics into nanometer scale regime and towards higher integration, several novel electronic devices are described here for computation and data storage applications. These include super-self-aligned separately-gated double-gate transistors, a cross-coupled bipolar injection memory (xFET) and top/back-gate carbon nanotube transistors. Hybrid integration of silicon and carbon nanotube electronics are demonstrated for the first time to show a viable direction for future electronics to extend technology reach for new scientific and engineering fields. The Super-self-aligned separately-gated double-gate field-effect transistor (FET), featuring strained silicon channel, thick source-drain region and buried-interconnected gate, have been made for both polarities n- and p-type using a novel approach that helps advance silicon CMOS technology to nanometer scale. All these features help alleviate the power consumption issues for future nanoscale CMOS transistor where performance degrades due to short channel effects and the loss of device threshold voltage control. A novel non-volatile memory device?xFET?is developed with several charge injection mechanisms to allow a variety of operational capabilities and provide significantly faster programming/erasing speed. Nanoseconds programming time has been achieved through hot electron injection. In a crossed nFET/pFET configuration, the new device features a four-terminal bipolar structure with a top floating gate used as the charge storage node. The silicon-on-insulator (SOI) technology in the device development ensures excellent CMOS compatibility. With techniques borrowed from silicon ULSI technology, carbon nanotube field-effect transistor (CNFET) with either back-gate or self-aligned top-gate structure has been developed to improve device performance and integration. For back-gate CNFET, combined analysis of device?s transient and transfer characteristics in contrasting environment (in air or in vacuum) show distinct ambient effects on the device carrier transport properties. High frequency pulse measurement is employed to produce intrinsic device transport properties through elimination of hysteresis and 1/f noise. Integration of carbon nanotubes transistor on top of nMOS transistors can provide compact circuit components. One example?a logic NOT gate is demonstrated in a monolithic integration of p-CNFET on top of nMOSFET. This integration scheme is an example that combine different technologies to make new applications possible on a robust silicon technology platform.en_US
dc.description.sponsorshipCenter for Nanoscale System National Science Foundationen_US
dc.format.extent17804005 bytes
dc.format.mimetypeapplication/pdf
dc.language.isoen_USen_US
dc.subjectsuper-self-aligned double-gateen_US
dc.subjectback-gateen_US
dc.subjectstrained silicon channelen_US
dc.subjectxFETen_US
dc.subjectthreshold voltage tuningen_US
dc.subjectadaptive power controlen_US
dc.subjectdual-polarity injectionen_US
dc.subjectnanosecond programming timeen_US
dc.subjectField Effect Transistoren_US
dc.subjectnonvolatile memoryen_US
dc.subjectcarbon nanotube field effect transistoren_US
dc.subjectHybrid Si/C integrated systemen_US
dc.subjecthysteresisen_US
dc.subjectpulse measurementen_US
dc.titleNOVEL SILICON AND CARBON NANOTUBE ELECTRONIC DEVICES: TECHNOLOGY, STRUCTURE AND PROPERTIESen_US
dc.typedissertation or thesisen_US


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