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dc.contributor.authorWeber, Samen_US
dc.contributor.authorBloom, Barden_US
dc.contributor.authorBrown, Geoffreyen_US
dc.date.accessioned2007-04-23T18:05:42Z
dc.date.available2007-04-23T18:05:42Z
dc.date.issued1996-01en_US
dc.identifier.citationhttp://techreports.library.cornell.edu:8081/Dienst/UI/1.0/Display/cul.cs/TR96-1566en_US
dc.identifier.urihttps://hdl.handle.net/1813/7223
dc.description.abstractManually designing delay-insensitive electronic circuits has proven to be difficult in practice. As an alternative, we designed and implemented a compiler that automatically produces such circuits. The source language for the compiler is a language called "Joy", which is a simple but complete parallel language with a syntax similar to that of many procedural languages. The compiler's output is a netlist suitable for input into standard place-and-route tools. In this paper, we present the highlights of the compilation algorithm, and the proof of correctness for it. This is among the first formally verified algorithms for compiling a general language into circuits.en_US
dc.format.extent383248 bytes
dc.format.extent561529 bytes
dc.format.mimetypeapplication/pdf
dc.format.mimetypeapplication/postscript
dc.language.isoen_USen_US
dc.publisherCornell Universityen_US
dc.subjectcomputer scienceen_US
dc.subjecttechnical reporten_US
dc.titleCompiling Joy Into Silicon: a Formally Verified Compiler forDelay-Insensitive Circuitsen_US
dc.typetechnical reporten_US


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