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dc.contributor.authorHua, Wenmian
dc.date.accessioned2020-08-10T20:24:03Z
dc.date.available2020-08-10T20:24:03Z
dc.date.issued2020-05
dc.identifier.otherHua_cornellgrad_0058F_11964
dc.identifier.otherhttp://dissertations.umi.com/cornellgrad:11964
dc.identifier.urihttps://hdl.handle.net/1813/70398
dc.description141 pages
dc.description.abstractAsynchronous circuits have potential advantages of higher speed and lower power consumption compared to their synchronous counterparts, but their poor CAD support is a major issue limiting adoption. A key component of any CAD flow for chip design is timing analysis, and the timing analysis problem for asynchronous logic is much more complicated than that for synchronous logic. Previous work on timing showed that such systems under AND-causality and fixed delay exhibit periodicity properties. In this thesis, we first give a graph-based proof of the exact periodicity properties of such systems. Our result under weaker assumption of system connectivity, provides a theoretical foundation for these properties to be applied and exploited in more general asynchronous circuits containing bundled data logic or synchronous components. Based on the theoretical results, we present the first known integrated timing and power analysis engine capable of handling large asynchronous timing circuits. For timing, we introduce the notion of performance and correctness slack for asynchronous circuits; for power, we compute both the static and dynamic components. We provide a hierarchical approach to constructing the event-dependency graph, and use the Galois framework for the parallelization to achieve fast runtime. The net result is Cyclone, a fast and accurate engine for both static timing and power analysis of asynchronous circuits. Along the way, we also explore the problem of cycle time of min-max system, one of the important algorithmic problems that we will encounter when extending our timing analysis to more general systems that contain OR-causality. We provide a new algorithm to solve this problem and prove its correctness. We also show that the algorithm runs reasonably fast in practice.
dc.language.isoen
dc.subjectasynchronous circuits
dc.subjectcomputational modeling
dc.subjectgraph theory
dc.subjectmetastability-free interface
dc.subjectmin-max systems
dc.subjecttiming analysis
dc.titleCyclone: The First Integrated Timing and Power Engine for Asynchronous Systems
dc.typedissertation or thesis
thesis.degree.disciplineElectrical and Computer Engineering
thesis.degree.grantorCornell University
thesis.degree.levelDoctor of Philosophy
thesis.degree.namePh. D., Electrical and Computer Engineering
dc.contributor.chairManohar, Rajit
dc.contributor.committeeMemberZhang, Zhiru
dc.contributor.committeeMemberStuder, Christoph
dcterms.licensehttps://hdl.handle.net/1813/59810
dc.identifier.doihttps://doi.org/10.7298/wynk-4987


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