Design and Analysis of Supply-Scaled Distributed Power Amplifiers

Abstract

Three distributed power amplifier topologies are developed for use in radio frequency (RF) front-ends. For viable integration in software-defined radios (SDR), the RF front-end must support operation over a wide range of tunable frequencies and duplex modulation schemes. This remains an unsolved challenge for circuit designers, and is the objective for the designs presented in this thesis. Two fully-integrated distributed power amplifier designs are developed in a 130nm SOI process. An on-chip artificial transmission line forms a path for the output current of each of the six power amplifier (PA) stages to constructively add at the antenna port. The initial design utilized class-A PA stages. To optimize power consumption, the second design implemented a supply-scaled class-AB distributed amplifier. The simulated power added efficiency (PAE) is 18.7% for an output power of 24.4 dBm, when source degenerated. Simulated power dissipation is 1.29 W from a 7.0 V supply. The measured output-referred 1 dB compression point and third-order intercept points are 9 dBm and 16 dBm, respectively. A third distributed amplifier design used a bulk CMOS 180nm process. Compared to an SOI process, the CMOS substrate is relatively lossy. Consequently, the design and discussion focused on using the systematic gm/ID design methodology to investigate circuit design trade-offs and optimize performance.