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dc.contributor.authorKhiyabani, Somayeh
dc.identifier.otherbibid: 10361448
dc.description.abstractMm-wave and terahertz frequency range is gaining vast attention in recent years due to attractive applications in various areas including spectroscopy, imaging, security and high data-rare communication. All these systems require high performance circuits for power generation and amplification. In recent years, many amplifiers and oscillators have been fabricated in SiGe and CMOS processes to show the feasibility of implementing these systems in this frequency range. Despite all the efforts and ideas employed to enhance the performance of these blocks, there is still a long way to go to achieve reasonably high performance amplifiers and signal sources at mm-wave and terahertz frequencies. The main challenge comes from the activity degradation of the transistors, high loss in the passives and high noise in the active and passive devices at this frequency range. In this work, new systematic design methods for low noise and highgain amplifiers and high power and efficiency oscillators at mm-wave and terahertz frequencies are presented. Chapter 1 reviews the basic concepts of the two-port networks such as stability, activity, power gains and noise parameters. These subjects are vastly used in the next chapters of this work when presenting the new methods for high frequency circuit design. In chapter 2, a new convex stability region is presented based on which, a systemic amplifier design method beyond fmax/2 is proposed which moves the network toward the high gain region using optimum passive embeddings. This method is capable of considering modeling errors of the components during the design process which results in a robust, stable and high gain amplifier. Employing this method, a three stage amplifier working at 173 GHz is designed and implemented in a 130 nm SiGe process which shows 18.5 dB gain, 8.2 GHz 3-dB bandwidth and 0.9 dBm saturated output power in the measurement. A new FoM is defined to fairly compare different amplifiers fabricatedindifferentprocesseswhichtargetsthecapabilityofthedesignmethodinextracting the power amplification potential of the active device. This amplifier achieves the highest FoM among all reported state of the arts works above fmax/2 in SiGe/CMOS processeswhichshowstheefficacyoftheproposedmethodinfullyutilizingtheprocess capabilities in amplifier design. In chapter 3, high frequency LNA is targeted and a systematic method to design low noise and high gain amplifier beyond fT/2 is presented. To achieve this goal, noise measure of the proposed structure becomes minimum employing optimum passive embeddings while the stability of the circuit is assured using the convex stability region derived in chapter 2. The guidelines and required noise and power equations to complete the systematic LNA design are derived and presented in this chapter. Employing this method,a 91 GHz LNA with 5.6dB noise figure,9.7 dB gain and 6.3 mW dc power consumption is implemented in a 130nm SiGe process. Comparing these results with the state of the arts using the proposed FoM that takes the process and power consumption into account justifies the effectiveness of this design method in fully utilizing low noise and high power generation capability of the process. A design methodology for high power mm-wave VCO design is presented in chapter 4. Using the complete passive embeddings including the load, the power gain from the input of the active device to the load is maximized which results in an oscillator with high power at the output and significantly improved DC-to-RF efficiency. In addition, the proposed structure is capable of providing sufficient tuning range which is an important factor in mm-wave source design and applications. A VCO working at 110 GHz is designed and implemented in a 55 nm SiGe process employing this method which shows 6.3 dBm peak output power, 20.9% DC-to-RF efficiency and 5.2% tuning range. This VCO achieves highest peak output power in F and D band (90 GHz to 170 GHz) and highest DC-to-RF efficiency in frequencies below fmax/2 among all reported mm-wave oscillators in SiGe/CMOS processes. Chapter 5 represents a new design method for high power and efficiency harmonic oscillator. This method exploits different mechanism to enhance the fundamental oscillator performance, increasing the harmonic power generation in the active device and effectively delivering the generated harmonic power to the load using various passive embeddings in a cross-coupled structure. Capacitive degeneration is employed to shape Gm of the structure. Inductive embeddings at the base of the transistors are utilized to provide sufficient voltage gain and increase harmonic current generation in the active device. The embeddings at the collector are used to maximize the output resistance of the structure which results in delivering majority of the generated current to the load. Employing this method, a 300 GHz harmonic oscillator is designed and implemented in a 130 nm SiGe process which shows 2.8 dBm peak output power and 4.5% DC-to-RF efficiency with 86.6 mW/mm2 power-area efficiency. Also, a harmonic VCO is implemented with 2.3 dBm peak output power, 3.5% DC-to-RF efficiency and 1.5% tuning range and 77.2 mW/mm2 power-area efficiency in the same process. This harmonic oscillator method significantly improves the power-area efficiency of high frequency signal sources and the designed oscillator achieves the highest power-area efficiency among all reported SiGe/CMOS oscillators working above 0.75 fmax.
dc.subjectHigh frequency circuit
dc.subjectmm-wave and Terahertz
dc.subjectHarmonic Oscillator
dc.typedissertation or thesis and Computer Engineering University of Philosophy D., Electrical and Computer Engineering
dc.contributor.chairAfshari, Ehsan
dc.contributor.committeeMemberApsel, Alyssa B.
dc.contributor.committeeMemberPollock, Clifford Raymond

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