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dc.contributor.authorHill, Benjamin
dc.date.accessioned2016-04-04T18:04:56Z
dc.date.available2021-02-01T07:00:50Z
dc.date.issued2016-02-01
dc.identifier.otherbibid: 9596969
dc.identifier.urihttps://hdl.handle.net/1813/43569
dc.description.abstractThe current slowdown in CMOS technology scaling presents opportunities for architectural innovation, in particular augmentation of general purpose processors with specialized units. Self-timed field-programmable gate arrays (FPGAs) are attractive in this space because of their high throughput, robustness, and modularity. In my thesis, I present an architecture for a dynamically reconfigurable asynchronous field-programmable gate array, describe efforts to limit the overheads of asynchronous communication in the context of 3D integration, and develop an asynchronous-aware toolflow for mapping designs to the FPGA.
dc.language.isoen_US
dc.titleArchitecture And Synthesis For Dynamically Reconfigurable Asynchronous Fpgas
dc.typedissertation or thesis
thesis.degree.disciplineElectrical Engineering
thesis.degree.grantorCornell University
thesis.degree.levelDoctor of Philosophy
thesis.degree.namePh. D., Electrical Engineering
dc.contributor.chairManohar,Rajit
dc.contributor.committeeMemberCrawford,Barbara A
dc.contributor.committeeMemberBatten,Christopher
dc.contributor.committeeMemberAlbonesi,David H.


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