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dc.contributor.authorFerraiuolo, Andrew
dc.contributor.authorWang, Yao
dc.contributor.authorXu, Rui
dc.contributor.authorZhang, Danfeng
dc.contributor.authorMyers, Andrew
dc.contributor.authorSuh, Edward
dc.date.accessioned2017-04-25T14:30:52Z
dc.date.available2015-11-10T19:26:25Z
dc.date.available2017-04-25T14:30:52Z
dc.date.issued2017-04-25
dc.identifier.urihttps://hdl.handle.net/1813/41218
dc.description.abstractThis paper presents timing compartments, a hardware architecture abstraction that eliminates microarchitectural timing channels between groups of processes of VMs running on shared hardware. When coupled with conventional access controls, timing compartments provide strong isolation comparable to running software entities on separate machines. Timing compartments use microarchitecture mechanisms to enforce timing sensitive noninterference, which we prove formally through information flow analysis of an RTL implementation. In the process of systematically removing timing interference, we identify and remove new sources of timing channels, including cache coherence mechanisms and module interfaces, and introduce new performance optimizations. We also demonstrate how timing compartments may be extended to support a hardware-only TCB which ensures security even when the system is managed by an untrusted OS or hypervisor. The overheads of timing compartments are low; compared to a comparable insecure baseline, executing two timing compartments reduces system throughput by less than 7% on average and by less than 2% for compute-bound workloads.en_US
dc.language.isoen_USen_US
dc.relation.replaceshttp://hdl.handle.net/1813/41218.1
dc.subjecttiming channelsen_US
dc.subjectinformation flowen_US
dc.subjectsecure processorsen_US
dc.titleFull-Processor Timing Channel Protection with Applications to Secure Hardware Compartmentsen_US
dc.typearticle


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