Analysis Of Process Variation On Nand Flash Memory

Abstract

Process variation in nanofabrication is the critical issue in both reliability and yield enhancement. Efforts in design and fabrication are applied to minimize the variation. Thus, detailed understanding about the influence from variation factors could help further development on scaling technology. Another main application in nanofabrication industry is the mass storage device. Solid-state drive (SSD), consisted of NAND Flash cell array, is considered as a promising solution for the rising demands in storage and cloud computing. Generally speaking, NAND Flash memory cell would have larger variations observed from external circuits, which makes it easier to approach. This fact motivated us to start analyzing the variation factors on NAND Flash memory performance and their applications in security function. In this thesis, we started with the simulation of NAND Flash device to acount for the dependence of line edge roughness (LER) on the floating gate. Then, we took the program time in each bit as a measure of variation. By doing specific sampling on target bits, we could de-couple the contribution from different factors as in-fabrication (Random Dopant Fluctuation), in-operation (Random Telegraph Noise) and layout dependence from chip measurement. Finally, we isolate each variation factor and demonstrate layout authentication from different technologies.