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dc.contributor.authorLockhart, Derek
dc.date.accessioned2015-10-15T18:01:11Z
dc.date.available2015-10-15T18:01:11Z
dc.date.issued2015-08-17
dc.identifier.otherbibid: 9255182
dc.identifier.urihttps://hdl.handle.net/1813/40914
dc.description.abstractThe growing complexity and heterogeneity of modern application-specific integrated circuits has made hardware design methodologies a limiting factor in the construction of future computing systems. This work aims to alleviate some of these design challenges by embedding productive hardware modeling and design constructs in general-purpose, high-level languages such as Python. Leveraging Python-based embedded domain-specific languages (DSLs) can considerably improve designer productivity over traditional design flows based on hardware-description languages (HDLs) and C++, however, these productivity benefits can be severely impacted by the poor execution performance of Python simulations. To address these performance issues, this work combines Python-based embedded-DSLs with just-in-time (JIT) optimization strategies to generate high-performance simulators that significantly reduce this performance-productivity gap. This thesis discusses two frameworks I have constructed that use this novel design approach: PyMTL, a Python-based, concurrent-structural modeling framework for vertically integrated hardware design, and Pydgin, a framework for generating high-performance, just-in-time optimizing instruction set simulators from high-level architecture descriptions.
dc.language.isoen_US
dc.subjectHardware Design Methodologies
dc.subjectComputer Architecture
dc.subjectVLSI
dc.titleConstructing Vertically Integrated Hardware Design Methodologies Using Embedded Domain-Specific Languages And Just-In-Time Optimization
dc.typedissertation or thesis
thesis.degree.disciplineElectrical Engineering
thesis.degree.grantorCornell University
thesis.degree.levelDoctor of Philosophy
thesis.degree.namePh. D., Electrical Engineering
dc.contributor.chairBatten,Christopher
dc.contributor.committeeMemberZhang,Zhiru
dc.contributor.committeeMemberManohar,Rajit


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