Show simple item record

dc.contributor.authorLongfield, Stephen
dc.date.accessioned2015-08-20T20:57:05Z
dc.date.available2020-05-24T06:01:22Z
dc.date.issued2015-05-24
dc.identifier.otherbibid: 9255470
dc.identifier.urihttps://hdl.handle.net/1813/40716
dc.description.abstractSelf-timed circuits have recently regained active interest as their abilities in avoiding timing and voltage margins, disconnecting pipeline depth from occupancy, and achieving average-case performance can help mitigate the challenges of very deep sub-micron design. However, there has been limited industrial adoption of these techniques, significantly due to the lack of commercial Computer Aided Design (CAD) support for synthesis and verification. This thesis presents a novel verification technique for the Quasi Delay-Insensitive (QDI) family of self-timed circuits leveraging properties of these circuits to reconstruct specifications from their implementations, using very little designer effort. The technique is presented in three stages: first, how to extract synchronization information from the gatelevel description, second, a type-and-effect system for ensuring stability and noninterference in the synchronization protocols, and lastly, a method for removing concurrency while maintaining the implementation relation of interest.
dc.language.isoen_US
dc.subjectVLSI
dc.subjectVerification
dc.subjectAsynchronous
dc.titleConstructive Verification Of Quasi Delay-Insensitive Circuits
dc.typedissertation or thesis
thesis.degree.disciplineElectrical Engineering
thesis.degree.grantorCornell University
thesis.degree.levelDoctor of Philosophy
thesis.degree.namePh. D., Electrical Engineering
dc.contributor.chairManohar,Rajit
dc.contributor.committeeMemberMyers,Andrew C.
dc.contributor.committeeMemberKozen,Dexter Campbell


Files in this item

Thumbnail

This item appears in the following Collection(s)

Show simple item record

Statistics