Applications at frequencies ranging from sub-millimeter wave to THz (100GHz to 1THz) are gaining a lot of attention. High frequencies can be employed for submillimeter wave astronomy in the field of heterodyne spectroscopy, sensing and imaging for security and detection of concealed weapons and explosives. Because of the lower fmax of solid state active devices, scaling of low frequency electronics to high frequencies is very challenging. At the same time, it is very difficult to make efficient semiconductor lasers of wavelength lower than 30[MICRO SIGN]m. Because of the dearth of high power and tunable sources at these frequencies, this part of spectrum is usually called "THz gap". Over the past few years, tremendous effort has been made towards solid-state THz sources. The world is looking for CMOS solutions to this problem because of the low cost of fabrication and ease of integration. The challenge in CMOS is low quality factor of passives, lossy substrate and limited fmax of the transistors which is still under 300GHz. To overcome these challenges two kinds of signal generation techniques at high frequencies are employed. 1) Frequency multiplication. 2) Collecting higher order harmonics from the fundamental VCO. Owing to these two signal generation technique, my research has been focused on both frequency multipliers and oscillators. In recent literature, few high frequency oscillators works are reported. However the major challenge has been to achieve high power and high tunability both at the same time with decent DC-RF efficiency. Since higher harmonic power is strongly dependent on the fundamental power, I have decomposed this problem in to two parts. 1) Coming up with a VCO topology that is capable of providing high tunability along with high power and DC-RF efficiency at fundamental frequency. 2) Efficiently extracting harmonics from the VCO without affecting operation at fundamental frequency. First two chapters discusses our work on these two parts. In chapter 1, a loop of unidirectionally coupled oscillators to demonstrate high tuning range and output power is proposed. To achieve large tuning range, two different tuning mechanisms are simultaneously exploited. First each core oscillator is tuned using a variable capacitor. Next, by controlling the phase/delay between the coupled oscillators, the entire loop dynamics and hence its frequency is tuned. In this work, we analyze a loop of "n" coupled oscillators using Adler's equation and derive the expression for the maximum tuning range. Perturbation analysis is used to study the stability conditions of the loop of coupled system. Activity condition from two port theory is also employed to squeeze maximum power out of active devices. The proposed system is designed and implemented using four coupled Colpitts VCOs in a 65nm bulk CMOS process. The VCO achieves continuous tuning range of 9.5% at the center frequency of 105GHz with the peak output power of 2.8mW. The circuit consumes 54mW from a 1.2V supply. To the best of our knowledge, this VCO has the highest output power and tuning range among all the CMOS oscillators at or above 100GHz. In chapter 2, we employ a loop of unidirectionally coupled harmonic oscillators. To accomplish large tunability, tuning via variable capacitance and via variable coupling delay between oscillators are simultaneously exploited. A large fundamental power to produce high second harmonic is generated using activity condition of the transistors derived through two port theory. All the undesired leakage of second harmonic current is blocked thus extracting maximum power at the output. A passive coupling between VCOs is employed to enhance DC-RF efficiency. Each oscillator is realized with modified self-feeding Colpitts architecture. To demonstrate our methodology, a two stage and an eight stage second harmonic VCOs are designed and fabricated in a 65nm bulk CMOS process. The 2-stage and 8-stage VCO achieves maximum power of -2.1dBm and 3.7dBm with DC-RF efficiency of 0.9% and 0.8%. Both VCO achieve tuning range of 8.6% at 260GHz. The two stage and eight stage VCO consume 198mA and 49mA from a 1.2V DC supply. To the best of our knowledge, these VCOs have the highest output power, tuning range and DC-RF efficiency among all the CMOS oscillators at or above 0.25THz. Chapter 3 and 4 deal with the frequency multipliers. Our research on frequency multipliers is focused on passive nonlinear transmission line (NLTL) based structures. In chapter 3, we develop a methodology of phase matching using bandgap transmission lines between the fundamental input and higher harmonics . We demonstrate the proposed methodology using a board level prototype that produces second harmonic with conversion loss of 5.5dB. Chapter 4 extends the concept proposed in chapter 3 for implementation in CMOS. Two methodologies are developed to go beyond the limitations of multipliers: i) we used bandgap structure to resolve dispersion which is inherently present in any discrete wave propagating structure. ii) in order to enhance conversion loss performance and relax input power requirement, we employ a resonator approach in combination with active loading. We build two prototypes: a 20GHz frequency doubler is implemented in a 65nm process as a proof of concept, second to show the feasibility of our approach near fmax , a 100GHz frequency tripler is implemented in a 130nm process. The achieved conversion loss is 3.5dB for doubler and 12.2dB in case of tripler. Both structures take single ended input and generate differential output. The frequency tripler can generate maximum power better than -1.5dBm. The relative bandwidth of doubler and tripler is about 23% and 12.3%. The frequency tripler outperforms any previously reported work in terms of output power and 3dB bandwidth at the same technology node.