INTEGRATION OF CARBON AND SILICON BASED NANOELECTRONICS
Nonvolatile memory technology has shown tremendous technological progress in the recent years. With the need for every higher memory density, the EEPROM structure has been subjected to aggressive scaling. Currently 65 nm devices are hitting production where the floating gate has been replaced by nitride traps for continued scaling. However the operational voltage has not scaled as aggressively. In this dissertation, various different structural variations of the EEPROM have been explored from experimental and theoretical perspectives. The electrostatics of nanocrystal memories with both metal and semiconductor nanocrystals have been analytically modeled to demonstrate enhanced field asymmetry in the path of least action in tunneling oxide. The larger polarization of the metal nanocrystal versus a semiconductor nanocrystal has been used to explain faster programming for metal nanocrystal memories compared to the semiconductor nanocrystal variety. The analytical model provides design intuition unlike numerical models for structural optimization. To provide a solution for the size-dependent variation of coulomb blockade self-assembled nanocrystals, molecules have been suggested as nano-floating gates in non-volatile memory. Carbon molecules like fullerenes (C60) have been integrated in the MOS gate stack. Charge injection into molecular orbital has been observed as repeatable steps in electron injection versus charging voltage data to demonstrate a successful molecular interface with CMOS. Finally, an ultra-narrow channel memory device fashioned out of self ?assembled carbon nanotube (CNT) channel with self aligned metal nanocrystals is proposed as an alternative to memory scaling. The device demonstrates large memory window and single-electron sensitivity. The single electron sensitivity at room temperature is confirmed by analysis of the transport in the CNT channel using non-equilibrium Green?s function (NEGF) formalism. The large number of charges stored in the nanocrystal at sub-5V gate bias for the 100 nm gate stack is demonstrated experimentally and explained from the electrostatic analysis of the CNT-nanocrystal memory. The ability to store large number of charges per nanocrystal and the ability of sense each of these charge charges indicates the possibility of a multi-level memory, a way of enhancing functional density while relaxing conventional memory scaling constraints.
Nanoelectronics; carbon nanotube; Nanocrystal; non-volatile memory; Traps; Tunneling; electrostatics
dissertation or thesis