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dc.contributor.authorLee, Wooramen_US
dc.date.accessioned2013-01-31T19:44:37Z
dc.date.available2017-12-20T07:00:28Z
dc.date.issued2012-08-20en_US
dc.identifier.otherbibid: 7959937
dc.identifier.urihttps://hdl.handle.net/1813/31174
dc.description.abstractAs Moore's law predicted, transistor scaling has continued unabated for more than half a century, resulting in significant improvement in speed, efficiency, and integration level. This has led to rapid growth of diverse computing and communications technologies, including the Internet and mobile telephony. Nevertheless, we still face the fundamental limit of noise from transistors and passive components. This noise limit becomes more critical at higher frequencies due to the decrease in intrinsic transistor gain as well as with voltage scaling that accompanies the transistor scaling. On the other hand, insufficient transistor gain and breakdown in silicon limits high-power signal generation at sub-millimeter frequencies that is essential in many security and medical applications, including detection of concealed weapons and bio/molecular spectroscopy for drug detection and breath analysis for disease diagnosis. To go beyond these limits, we propose a new circuit design methodology inspired by nonlinear wave propagation. This method is closely related to intriguing phenomena in other disciplines of physics such as nonlinear optics, fluid mechanics, and plasma physics. Based on this, in the first part of this study, we propose a passive 20-GHz frequency divider for the first time implemented in CMOS. This device has close to ideal noise performance with no DC power consumption, which can potentially reduce overall system power and phase noise in high-frequency synthesizers. Next, to achieve sensitivity toward the thermal noise limit, we propose a 10-GHz CMOS noise-squeezing amplifier. This amplifier enhances sensitivity of an input signal in one quadrature phase by 2.5 dB at the expense of degrading the other quadrature component. Lastly, we introduce an LC lattice to generate 2.7 V p[-] p , 6 ps pulses in CMOS using constructive nonlinear wave interaction. The proposed lattice exhibits the sharpest pulse width achieved for high-amplitude pulses (>1 V) in any CMOS processes.en_US
dc.language.isoen_USen_US
dc.subjectIntegrated Circuitsen_US
dc.subjectNonlinearen_US
dc.subjectcmosen_US
dc.titleNonlinear Circuits For Signal Generation And Processing In Cmosen_US
dc.typedissertation or thesisen_US
thesis.degree.disciplineElectrical Engineering
thesis.degree.grantorCornell Universityen_US
thesis.degree.levelDoctor of Philosophy
thesis.degree.namePh. D., Electrical Engineering
dc.contributor.chairAfshari, Ehsanen_US
dc.contributor.committeeMemberApsel, Alyssa B.en_US
dc.contributor.committeeMemberGaeta, Alexander L.en_US
dc.contributor.committeeMemberPollock, Clifford Raymonden_US


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